1 /** 2 Based on IndustryStandard/Acpi40.h, original notice: 3 4 ACPI 4.0 definitions from the ACPI Specification Revision 4.0a April 5, 2010 5 6 Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved. 7 This program and the accompanying materials 8 are licensed and made available under the terms and conditions of the BSD License 9 which accompanies this distribution. The full text of the license may be found at 10 http://opensource.org/licenses/bsd-license.php 11 12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 14 **/ 15 module uefi.acpi40; 16 import uefi.base; 17 import uefi.base_type; 18 import uefi.acpiaml; 19 import uefi.acpi10; 20 import uefi.acpi20; 21 import uefi.acpi30; 22 23 public: 24 extern (C): 25 26 /// ACPI 4.0 Generic Address Space definition 27 struct EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE 28 { 29 align(1): 30 UINT8 AddressSpaceId; 31 UINT8 RegisterBitWidth; 32 UINT8 RegisterBitOffset; 33 UINT8 AccessSize; 34 UINT64 Address; 35 } 36 37 enum EFI_ACPI_4_0_SYSTEM_MEMORY = 0; 38 enum EFI_ACPI_4_0_SYSTEM_IO = 1; 39 enum EFI_ACPI_4_0_PCI_CONFIGURATION_SPACE = 2; 40 enum EFI_ACPI_4_0_EMBEDDED_CONTROLLER = 3; 41 enum EFI_ACPI_4_0_SMBUS = 4; 42 enum EFI_ACPI_4_0_FUNCTIONAL_FIXED_HARDWARE = 0x7F; 43 enum EFI_ACPI_4_0_UNDEFINED = 0; 44 enum EFI_ACPI_4_0_BYTE = 1; 45 enum EFI_ACPI_4_0_WORD = 2; 46 enum EFI_ACPI_4_0_DWORD = 3; 47 enum EFI_ACPI_4_0_QWORD = 4; 48 /// Root System Description Pointer Structure 49 struct EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_POINTER 50 { 51 align(1): 52 UINT64 Signature; 53 UINT8 Checksum; 54 UINT8[6] OemId; 55 UINT8 Revision; 56 UINT32 RsdtAddress; 57 UINT32 Length; 58 UINT64 XsdtAddress; 59 UINT8 ExtendedChecksum; 60 UINT8[3] Reserved; 61 } 62 /// RSD_PTR Revision (as defined in ACPI 4.0b spec.) 63 enum EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION = 0x02; ///< ACPISpec (Revision 4.0a) says current value is 2 64 /// Common table header, this prefaces all ACPI tables, including FACS, but 65 /// excluding the RSD PTR structure 66 struct EFI_ACPI_4_0_COMMON_HEADER 67 { 68 align(1): 69 UINT32 Signature; 70 UINT32 Length; 71 } 72 /// RSDT Revision (as defined in ACPI 4.0 spec.) 73 enum EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION = 0x01; 74 /// XSDT Revision (as defined in ACPI 4.0 spec.) 75 enum EFI_ACPI_4_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION = 0x01; 76 /// Fixed ACPI Description Table Structure (FADT) 77 struct EFI_ACPI_4_0_FIXED_ACPI_DESCRIPTION_TABLE 78 { 79 align(1): 80 EFI_ACPI_DESCRIPTION_HEADER Header; 81 UINT32 FirmwareCtrl; 82 UINT32 Dsdt; 83 UINT8 Reserved0; 84 UINT8 PreferredPmProfile; 85 UINT16 SciInt; 86 UINT32 SmiCmd; 87 UINT8 AcpiEnable; 88 UINT8 AcpiDisable; 89 UINT8 S4BiosReq; 90 UINT8 PstateCnt; 91 UINT32 Pm1aEvtBlk; 92 UINT32 Pm1bEvtBlk; 93 UINT32 Pm1aCntBlk; 94 UINT32 Pm1bCntBlk; 95 UINT32 Pm2CntBlk; 96 UINT32 PmTmrBlk; 97 UINT32 Gpe0Blk; 98 UINT32 Gpe1Blk; 99 UINT8 Pm1EvtLen; 100 UINT8 Pm1CntLen; 101 UINT8 Pm2CntLen; 102 UINT8 PmTmrLen; 103 UINT8 Gpe0BlkLen; 104 UINT8 Gpe1BlkLen; 105 UINT8 Gpe1Base; 106 UINT8 CstCnt; 107 UINT16 PLvl2Lat; 108 UINT16 PLvl3Lat; 109 UINT16 FlushSize; 110 UINT16 FlushStride; 111 UINT8 DutyOffset; 112 UINT8 DutyWidth; 113 UINT8 DayAlrm; 114 UINT8 MonAlrm; 115 UINT8 Century; 116 UINT16 IaPcBootArch; 117 UINT8 Reserved1; 118 UINT32 Flags; 119 EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE ResetReg; 120 UINT8 ResetValue; 121 UINT8[3] Reserved2; 122 UINT64 XFirmwareCtrl; 123 UINT64 XDsdt; 124 EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk; 125 EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk; 126 EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk; 127 EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk; 128 EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk; 129 EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk; 130 EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk; 131 EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk; 132 } 133 /// FADT Version (as defined in ACPI 4.0 spec.) 134 enum EFI_ACPI_4_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION = 0x04; 135 enum EFI_ACPI_4_0_PM_PROFILE_UNSPECIFIED = 0; 136 enum EFI_ACPI_4_0_PM_PROFILE_DESKTOP = 1; 137 enum EFI_ACPI_4_0_PM_PROFILE_MOBILE = 2; 138 enum EFI_ACPI_4_0_PM_PROFILE_WORKSTATION = 3; 139 enum EFI_ACPI_4_0_PM_PROFILE_ENTERPRISE_SERVER = 4; 140 enum EFI_ACPI_4_0_PM_PROFILE_SOHO_SERVER = 5; 141 enum EFI_ACPI_4_0_PM_PROFILE_APPLIANCE_PC = 6; 142 enum EFI_ACPI_4_0_PM_PROFILE_PERFORMANCE_SERVER = 7; 143 enum EFI_ACPI_4_0_LEGACY_DEVICES = BIT0; 144 enum EFI_ACPI_4_0_8042 = BIT1; 145 enum EFI_ACPI_4_0_VGA_NOT_PRESENT = BIT2; 146 enum EFI_ACPI_4_0_MSI_NOT_SUPPORTED = BIT3; 147 enum EFI_ACPI_4_0_PCIE_ASPM_CONTROLS = BIT4; 148 enum EFI_ACPI_4_0_WBINVD = BIT0; 149 enum EFI_ACPI_4_0_WBINVD_FLUSH = BIT1; 150 enum EFI_ACPI_4_0_PROC_C1 = BIT2; 151 enum EFI_ACPI_4_0_P_LVL2_UP = BIT3; 152 enum EFI_ACPI_4_0_PWR_BUTTON = BIT4; 153 enum EFI_ACPI_4_0_SLP_BUTTON = BIT5; 154 enum EFI_ACPI_4_0_FIX_RTC = BIT6; 155 enum EFI_ACPI_4_0_RTC_S4 = BIT7; 156 enum EFI_ACPI_4_0_TMR_VAL_EXT = BIT8; 157 enum EFI_ACPI_4_0_DCK_CAP = BIT9; 158 enum EFI_ACPI_4_0_RESET_REG_SUP = BIT10; 159 enum EFI_ACPI_4_0_SEALED_CASE = BIT11; 160 enum EFI_ACPI_4_0_HEADLESS = BIT12; 161 enum EFI_ACPI_4_0_CPU_SW_SLP = BIT13; 162 enum EFI_ACPI_4_0_PCI_EXP_WAK = BIT14; 163 enum EFI_ACPI_4_0_USE_PLATFORM_CLOCK = BIT15; 164 enum EFI_ACPI_4_0_S4_RTC_STS_VALID = BIT16; 165 enum EFI_ACPI_4_0_REMOTE_POWER_ON_CAPABLE = BIT17; 166 enum EFI_ACPI_4_0_FORCE_APIC_CLUSTER_MODEL = BIT18; 167 enum EFI_ACPI_4_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE = BIT19; 168 /// Firmware ACPI Control Structure 169 struct EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE 170 { 171 align(1): 172 UINT32 Signature; 173 UINT32 Length; 174 UINT32 HardwareSignature; 175 UINT32 FirmwareWakingVector; 176 UINT32 GlobalLock; 177 UINT32 Flags; 178 UINT64 XFirmwareWakingVector; 179 UINT8 Version; 180 UINT8[3] Reserved0; 181 UINT32 OspmFlags; 182 UINT8[24] Reserved1; 183 } 184 /// FACS Version (as defined in ACPI 4.0 spec.) 185 enum EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION = 0x02; 186 /// Firmware Control Structure Feature Flags 187 /// All other bits are reserved and must be set to 0. 188 enum EFI_ACPI_4_0_S4BIOS_F = BIT0; 189 enum EFI_ACPI_4_0_64BIT_WAKE_SUPPORTED_F = BIT1; 190 /// OSPM Enabled Firmware Control Structure Flags 191 /// All other bits are reserved and must be set to 0. 192 enum EFI_ACPI_4_0_OSPM_64BIT_WAKE__F = BIT0; 193 enum EFI_ACPI_4_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION = 0x02; 194 enum EFI_ACPI_4_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION = 0x02; 195 /// Multiple APIC Description Table header definition. The rest of the table 196 /// must be defined in a platform specific manner. 197 struct EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER 198 { 199 align(1): 200 EFI_ACPI_DESCRIPTION_HEADER Header; 201 UINT32 LocalApicAddress; 202 UINT32 Flags; 203 } 204 /// MADT Revision (as defined in ACPI 4.0 spec.) 205 enum EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION = 0x03; 206 /// Multiple APIC Flags 207 /// All other bits are reserved and must be set to 0. 208 enum EFI_ACPI_4_0_PCAT_COMPAT = BIT0; 209 enum EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC = 0x00; 210 enum EFI_ACPI_4_0_IO_APIC = 0x01; 211 enum EFI_ACPI_4_0_INTERRUPT_SOURCE_OVERRIDE = 0x02; 212 enum EFI_ACPI_4_0_NON_MASKABLE_INTERRUPT_SOURCE = 0x03; 213 enum EFI_ACPI_4_0_LOCAL_APIC_NMI = 0x04; 214 enum EFI_ACPI_4_0_LOCAL_APIC_ADDRESS_OVERRIDE = 0x05; 215 enum EFI_ACPI_4_0_IO_SAPIC = 0x06; 216 enum EFI_ACPI_4_0_LOCAL_SAPIC = 0x07; 217 enum EFI_ACPI_4_0_PLATFORM_INTERRUPT_SOURCES = 0x08; 218 enum EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC = 0x09; 219 enum EFI_ACPI_4_0_LOCAL_X2APIC_NMI = 0x0A; 220 /// Processor Local APIC Structure Definition 221 struct EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_STRUCTURE 222 { 223 align(1): 224 UINT8 Type; 225 UINT8 Length; 226 UINT8 AcpiProcessorId; 227 UINT8 ApicId; 228 UINT32 Flags; 229 } 230 /// Local APIC Flags. All other bits are reserved and must be 0. 231 enum EFI_ACPI_4_0_LOCAL_APIC_ENABLED = BIT0; 232 /// IO APIC Structure 233 struct EFI_ACPI_4_0_IO_APIC_STRUCTURE 234 { 235 align(1): 236 UINT8 Type; 237 UINT8 Length; 238 UINT8 IoApicId; 239 UINT8 Reserved; 240 UINT32 IoApicAddress; 241 UINT32 GlobalSystemInterruptBase; 242 } 243 /// Interrupt Source Override Structure 244 struct EFI_ACPI_4_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE 245 { 246 align(1): 247 UINT8 Type; 248 UINT8 Length; 249 UINT8 Bus; 250 UINT8 Source; 251 UINT32 GlobalSystemInterrupt; 252 UINT16 Flags; 253 } 254 /// Platform Interrupt Sources Structure Definition 255 struct EFI_ACPI_4_0_PLATFORM_INTERRUPT_APIC_STRUCTURE 256 { 257 align(1): 258 UINT8 Type; 259 UINT8 Length; 260 UINT16 Flags; 261 UINT8 InterruptType; 262 UINT8 ProcessorId; 263 UINT8 ProcessorEid; 264 UINT8 IoSapicVector; 265 UINT32 GlobalSystemInterrupt; 266 UINT32 PlatformInterruptSourceFlags; 267 UINT8 CpeiProcessorOverride; 268 UINT8[31] Reserved; 269 } 270 271 enum EFI_ACPI_4_0_POLARITY = (3 << 0); 272 enum EFI_ACPI_4_0_TRIGGER_MODE = (3 << 2); 273 /// Non-Maskable Interrupt Source Structure 274 struct EFI_ACPI_4_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE 275 { 276 align(1): 277 UINT8 Type; 278 UINT8 Length; 279 UINT16 Flags; 280 UINT32 GlobalSystemInterrupt; 281 } 282 /// Local APIC NMI Structure 283 struct EFI_ACPI_4_0_LOCAL_APIC_NMI_STRUCTURE 284 { 285 align(1): 286 UINT8 Type; 287 UINT8 Length; 288 UINT8 AcpiProcessorId; 289 UINT16 Flags; 290 UINT8 LocalApicLint; 291 } 292 /// Local APIC Address Override Structure 293 struct EFI_ACPI_4_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE 294 { 295 align(1): 296 UINT8 Type; 297 UINT8 Length; 298 UINT16 Reserved; 299 UINT64 LocalApicAddress; 300 } 301 /// IO SAPIC Structure 302 struct EFI_ACPI_4_0_IO_SAPIC_STRUCTURE 303 { 304 align(1): 305 UINT8 Type; 306 UINT8 Length; 307 UINT8 IoApicId; 308 UINT8 Reserved; 309 UINT32 GlobalSystemInterruptBase; 310 UINT64 IoSapicAddress; 311 } 312 /// Local SAPIC Structure 313 /// This struct followed by a null-terminated ASCII string - ACPI Processor UID String 314 struct EFI_ACPI_4_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE 315 { 316 align(1): 317 UINT8 Type; 318 UINT8 Length; 319 UINT8 AcpiProcessorId; 320 UINT8 LocalSapicId; 321 UINT8 LocalSapicEid; 322 UINT8[3] Reserved; 323 UINT32 Flags; 324 UINT32 ACPIProcessorUIDValue; 325 } 326 /// Platform Interrupt Sources Structure 327 struct EFI_ACPI_4_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE 328 { 329 align(1): 330 UINT8 Type; 331 UINT8 Length; 332 UINT16 Flags; 333 UINT8 InterruptType; 334 UINT8 ProcessorId; 335 UINT8 ProcessorEid; 336 UINT8 IoSapicVector; 337 UINT32 GlobalSystemInterrupt; 338 UINT32 PlatformInterruptSourceFlags; 339 } 340 /// Platform Interrupt Source Flags. 341 /// All other bits are reserved and must be set to 0. 342 enum EFI_ACPI_4_0_CPEI_PROCESSOR_OVERRIDE = BIT0; 343 /// Processor Local x2APIC Structure Definition 344 struct EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE 345 { 346 align(1): 347 UINT8 Type; 348 UINT8 Length; 349 UINT8[2] Reserved; 350 UINT32 X2ApicId; 351 UINT32 Flags; 352 UINT32 AcpiProcessorUid; 353 } 354 /// Local x2APIC NMI Structure 355 struct EFI_ACPI_4_0_LOCAL_X2APIC_NMI_STRUCTURE 356 { 357 align(1): 358 UINT8 Type; 359 UINT8 Length; 360 UINT16 Flags; 361 UINT32 AcpiProcessorUid; 362 UINT8 LocalX2ApicLint; 363 UINT8[3] Reserved; 364 } 365 /// Smart Battery Description Table (SBST) 366 struct EFI_ACPI_4_0_SMART_BATTERY_DESCRIPTION_TABLE 367 { 368 align(1): 369 EFI_ACPI_DESCRIPTION_HEADER Header; 370 UINT32 WarningEnergyLevel; 371 UINT32 LowEnergyLevel; 372 UINT32 CriticalEnergyLevel; 373 } 374 /// SBST Version (as defined in ACPI 4.0 spec.) 375 enum EFI_ACPI_4_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION = 0x01; 376 /// Embedded Controller Boot Resources Table (ECDT) 377 /// The table is followed by a null terminated ASCII string that contains 378 /// a fully qualified reference to the name space object. 379 struct EFI_ACPI_4_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE 380 { 381 align(1): 382 EFI_ACPI_DESCRIPTION_HEADER Header; 383 EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE EcControl; 384 EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE EcData; 385 UINT32 Uid; 386 UINT8 GpeBit; 387 } 388 /// ECDT Version (as defined in ACPI 4.0 spec.) 389 enum EFI_ACPI_4_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION = 0x01; 390 /// System Resource Affinity Table (SRAT. The rest of the table 391 /// must be defined in a platform specific manner. 392 struct EFI_ACPI_4_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER 393 { 394 align(1): 395 EFI_ACPI_DESCRIPTION_HEADER Header; 396 UINT32 Reserved1; ///< Must be set to 1 397 UINT64 Reserved2; 398 } 399 /// SRAT Version (as defined in ACPI 4.0 spec.) 400 enum EFI_ACPI_4_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION = 0x03; 401 enum EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY = 0x00; 402 enum EFI_ACPI_4_0_MEMORY_AFFINITY = 0x01; 403 enum EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_AFFINITY = 0x02; 404 /// Processor Local APIC/SAPIC Affinity Structure Definition 405 struct EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE 406 { 407 align(1): 408 UINT8 Type; 409 UINT8 Length; 410 UINT8 ProximityDomain7To0; 411 UINT8 ApicId; 412 UINT32 Flags; 413 UINT8 LocalSapicEid; 414 UINT8[3] ProximityDomain31To8; 415 UINT32 ClockDomain; 416 } 417 /// Local APIC/SAPIC Flags. All other bits are reserved and must be 0. 418 enum EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED = (1 << 0); 419 /// Memory Affinity Structure Definition 420 struct EFI_ACPI_4_0_MEMORY_AFFINITY_STRUCTURE 421 { 422 align(1): 423 UINT8 Type; 424 UINT8 Length; 425 UINT32 ProximityDomain; 426 UINT16 Reserved1; 427 UINT32 AddressBaseLow; 428 UINT32 AddressBaseHigh; 429 UINT32 LengthLow; 430 UINT32 LengthHigh; 431 UINT32 Reserved2; 432 UINT32 Flags; 433 UINT64 Reserved3; 434 } 435 436 enum EFI_ACPI_4_0_MEMORY_ENABLED = (1 << 0); 437 enum EFI_ACPI_4_0_MEMORY_HOT_PLUGGABLE = (1 << 1); 438 enum EFI_ACPI_4_0_MEMORY_NONVOLATILE = (1 << 2); 439 /// Processor Local x2APIC Affinity Structure Definition 440 struct EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE 441 { 442 align(1): 443 UINT8 Type; 444 UINT8 Length; 445 UINT8[2] Reserved1; 446 UINT32 ProximityDomain; 447 UINT32 X2ApicId; 448 UINT32 Flags; 449 UINT32 ClockDomain; 450 UINT8[4] Reserved2; 451 } 452 /// System Locality Distance Information Table (SLIT). 453 /// The rest of the table is a matrix. 454 struct EFI_ACPI_4_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER 455 { 456 align(1): 457 EFI_ACPI_DESCRIPTION_HEADER Header; 458 UINT64 NumberOfSystemLocalities; 459 } 460 /// SLIT Version (as defined in ACPI 4.0 spec.) 461 enum EFI_ACPI_4_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION = 0x01; 462 /// Corrected Platform Error Polling Table (CPEP) 463 struct EFI_ACPI_4_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER 464 { 465 align(1): 466 EFI_ACPI_DESCRIPTION_HEADER Header; 467 UINT8[8] Reserved; 468 } 469 /// CPEP Version (as defined in ACPI 4.0 spec.) 470 enum EFI_ACPI_4_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION = 0x01; 471 enum EFI_ACPI_4_0_CPEP_PROCESSOR_APIC_SAPIC = 0x00; 472 /// Corrected Platform Error Polling Processor Structure Definition 473 struct EFI_ACPI_4_0_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE 474 { 475 align(1): 476 UINT8 Type; 477 UINT8 Length; 478 UINT8 ProcessorId; 479 UINT8 ProcessorEid; 480 UINT32 PollingInterval; 481 } 482 /// Maximum System Characteristics Table (MSCT) 483 struct EFI_ACPI_4_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER 484 { 485 align(1): 486 EFI_ACPI_DESCRIPTION_HEADER Header; 487 UINT32 OffsetProxDomInfo; 488 UINT32 MaximumNumberOfProximityDomains; 489 UINT32 MaximumNumberOfClockDomains; 490 UINT64 MaximumPhysicalAddress; 491 } 492 /// MSCT Version (as defined in ACPI 4.0 spec.) 493 enum EFI_ACPI_4_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION = 0x01; 494 /// Maximum Proximity Domain Information Structure Definition 495 struct EFI_ACPI_4_0_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE 496 { 497 align(1): 498 UINT8 Revision; 499 UINT8 Length; 500 UINT32 ProximityDomainRangeLow; 501 UINT32 ProximityDomainRangeHigh; 502 UINT32 MaximumProcessorCapacity; 503 UINT64 MaximumMemoryCapacity; 504 } 505 /// Boot Error Record Table (BERT) 506 struct EFI_ACPI_4_0_BOOT_ERROR_RECORD_TABLE_HEADER 507 { 508 align(1): 509 EFI_ACPI_DESCRIPTION_HEADER Header; 510 UINT32 BootErrorRegionLength; 511 UINT64 BootErrorRegion; 512 } 513 /// BERT Version (as defined in ACPI 4.0 spec.) 514 enum EFI_ACPI_4_0_BOOT_ERROR_RECORD_TABLE_REVISION = 0x01; 515 /// Boot Error Region Block Status Definition 516 struct EFI_ACPI_4_0_ERROR_BLOCK_STATUS 517 { 518 align(1): 519 mixin(bitfields!(UINT32, "UncorrectableErrorValid", 1, UINT32, 520 "CorrectableErrorValid", 1, UINT32, "MultipleUncorrectableErrors", 1, 521 UINT32, "MultipleCorrectableErrors", 1, UINT32, "ErrorDataEntryCount", 522 10, UINT32, "Reserved", 18)); 523 } 524 /// Boot Error Region Definition 525 struct EFI_ACPI_4_0_BOOT_ERROR_REGION_STRUCTURE 526 { 527 align(1): 528 EFI_ACPI_4_0_ERROR_BLOCK_STATUS BlockStatus; 529 UINT32 RawDataOffset; 530 UINT32 RawDataLength; 531 UINT32 DataLength; 532 UINT32 ErrorSeverity; 533 } 534 535 enum EFI_ACPI_4_0_ERROR_SEVERITY_CORRECTABLE = 0x00; 536 enum EFI_ACPI_4_0_ERROR_SEVERITY_FATAL = 0x01; 537 enum EFI_ACPI_4_0_ERROR_SEVERITY_CORRECTED = 0x02; 538 enum EFI_ACPI_4_0_ERROR_SEVERITY_NONE = 0x03; 539 /// Generic Error Data Entry Definition 540 struct EFI_ACPI_4_0_GENERIC_ERROR_DATA_ENTRY_STRUCTURE 541 { 542 align(1): 543 UINT8[16] SectionType; 544 UINT32 ErrorSeverity; 545 UINT16 Revision; 546 UINT8 ValidationBits; 547 UINT8 Flags; 548 UINT32 ErrorDataLength; 549 UINT8[16] FruId; 550 UINT8[20] FruText; 551 } 552 /// Generic Error Data Entry Version (as defined in ACPI 4.0 spec.) 553 enum EFI_ACPI_4_0_GENERIC_ERROR_DATA_ENTRY_REVISION = 0x0201; 554 /// HEST - Hardware Error Source Table 555 struct EFI_ACPI_4_0_HARDWARE_ERROR_SOURCE_TABLE_HEADER 556 { 557 align(1): 558 EFI_ACPI_DESCRIPTION_HEADER Header; 559 UINT32 ErrorSourceCount; 560 } 561 /// HEST Version (as defined in ACPI 4.0 spec.) 562 enum EFI_ACPI_4_0_HARDWARE_ERROR_SOURCE_TABLE_REVISION = 0x01; 563 enum EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION = 0x00; 564 enum EFI_ACPI_4_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK = 0x01; 565 enum EFI_ACPI_4_0_IA32_ARCHITECTURE_NMI_ERROR = 0x02; 566 enum EFI_ACPI_4_0_PCI_EXPRESS_ROOT_PORT_AER = 0x06; 567 enum EFI_ACPI_4_0_PCI_EXPRESS_DEVICE_AER = 0x07; 568 enum EFI_ACPI_4_0_PCI_EXPRESS_BRIDGE_AER = 0x08; 569 enum EFI_ACPI_4_0_GENERIC_HARDWARE_ERROR = 0x09; 570 enum EFI_ACPI_4_0_ERROR_SOURCE_FLAG_FIRMWARE_FIRST = (1 << 0); 571 enum EFI_ACPI_4_0_ERROR_SOURCE_FLAG_GLOBAL = (1 << 1); 572 /// IA-32 Architecture Machine Check Exception Structure Definition 573 struct EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE 574 { 575 align(1): 576 UINT16 Type; 577 UINT16 SourceId; 578 UINT8[2] Reserved0; 579 UINT8 Flags; 580 UINT8 Enabled; 581 UINT32 NumberOfRecordsToPreAllocate; 582 UINT32 MaxSectionsPerRecord; 583 UINT64 GlobalCapabilityInitData; 584 UINT64 GlobalControlInitData; 585 UINT8 NumberOfHardwareBanks; 586 UINT8[7] Reserved1; 587 } 588 /// IA-32 Architecture Machine Check Bank Structure Definition 589 struct EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE 590 { 591 align(1): 592 UINT8 BankNumber; 593 UINT8 ClearStatusOnInitialization; 594 UINT8 StatusDataFormat; 595 UINT8 Reserved0; 596 UINT32 ControlRegisterMsrAddress; 597 UINT64 ControlInitData; 598 UINT32 StatusRegisterMsrAddress; 599 UINT32 AddressRegisterMsrAddress; 600 UINT32 MiscRegisterMsrAddress; 601 } 602 /// IA-32 Architecture Machine Check Bank Structure MCA data format 603 enum EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 = 0x00; 604 enum EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 = 0x01; 605 enum EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 = 0x02; 606 enum EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_POLLED = 0x00; 607 enum EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT = 0x01; 608 enum EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT = 0x02; 609 enum EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_SCI = 0x03; 610 enum EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_NMI = 0x04; 611 /// Hardware Error Notification Configuration Write Enable Structure Definition 612 struct EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE 613 { 614 align(1): 615 mixin(bitfields!(UINT16, "Type", 1, UINT16, "PollInterval", 1, UINT16, 616 "SwitchToPollingThresholdValue", 1, UINT16, 617 "SwitchToPollingThresholdWindow", 1, UINT16, "ErrorThresholdValue", 1, 618 UINT16, "ErrorThresholdWindow", 1, UINT16, "Reserved", 10)); 619 } 620 /// Hardware Error Notification Structure Definition 621 struct EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE 622 { 623 align(1): 624 UINT8 Type; 625 UINT8 Length; 626 EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable; 627 UINT32 PollInterval; 628 UINT32 Vector; 629 UINT32 SwitchToPollingThresholdValue; 630 UINT32 SwitchToPollingThresholdWindow; 631 UINT32 ErrorThresholdValue; 632 UINT32 ErrorThresholdWindow; 633 } 634 /// IA-32 Architecture Corrected Machine Check Structure Definition 635 struct EFI_ACPI_4_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE 636 { 637 align(1): 638 UINT16 Type; 639 UINT16 SourceId; 640 UINT8[2] Reserved0; 641 UINT8 Flags; 642 UINT8 Enabled; 643 UINT32 NumberOfRecordsToPreAllocate; 644 UINT32 MaxSectionsPerRecord; 645 EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure; 646 UINT8 NumberOfHardwareBanks; 647 UINT8[3] Reserved1; 648 } 649 /// IA-32 Architecture NMI Error Structure Definition 650 struct EFI_ACPI_4_0_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE 651 { 652 align(1): 653 UINT16 Type; 654 UINT16 SourceId; 655 UINT8[2] Reserved0; 656 UINT32 NumberOfRecordsToPreAllocate; 657 UINT32 MaxSectionsPerRecord; 658 UINT32 MaxRawDataLength; 659 } 660 /// PCI Express Root Port AER Structure Definition 661 struct EFI_ACPI_4_0_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE 662 { 663 align(1): 664 UINT16 Type; 665 UINT16 SourceId; 666 UINT8[2] Reserved0; 667 UINT8 Flags; 668 UINT8 Enabled; 669 UINT32 NumberOfRecordsToPreAllocate; 670 UINT32 MaxSectionsPerRecord; 671 UINT32 Bus; 672 UINT16 Device; 673 UINT16 Function; 674 UINT16 DeviceControl; 675 UINT8[2] Reserved1; 676 UINT32 UncorrectableErrorMask; 677 UINT32 UncorrectableErrorSeverity; 678 UINT32 CorrectableErrorMask; 679 UINT32 AdvancedErrorCapabilitiesAndControl; 680 UINT32 RootErrorCommand; 681 } 682 /// PCI Express Device AER Structure Definition 683 struct EFI_ACPI_4_0_PCI_EXPRESS_DEVICE_AER_STRUCTURE 684 { 685 align(1): 686 UINT16 Type; 687 UINT16 SourceId; 688 UINT8[2] Reserved0; 689 UINT8 Flags; 690 UINT8 Enabled; 691 UINT32 NumberOfRecordsToPreAllocate; 692 UINT32 MaxSectionsPerRecord; 693 UINT32 Bus; 694 UINT16 Device; 695 UINT16 Function; 696 UINT16 DeviceControl; 697 UINT8[2] Reserved1; 698 UINT32 UncorrectableErrorMask; 699 UINT32 UncorrectableErrorSeverity; 700 UINT32 CorrectableErrorMask; 701 UINT32 AdvancedErrorCapabilitiesAndControl; 702 } 703 /// PCI Express Bridge AER Structure Definition 704 struct EFI_ACPI_4_0_PCI_EXPRESS_BRIDGE_AER_STRUCTURE 705 { 706 align(1): 707 UINT16 Type; 708 UINT16 SourceId; 709 UINT8[2] Reserved0; 710 UINT8 Flags; 711 UINT8 Enabled; 712 UINT32 NumberOfRecordsToPreAllocate; 713 UINT32 MaxSectionsPerRecord; 714 UINT32 Bus; 715 UINT16 Device; 716 UINT16 Function; 717 UINT16 DeviceControl; 718 UINT8[2] Reserved1; 719 UINT32 UncorrectableErrorMask; 720 UINT32 UncorrectableErrorSeverity; 721 UINT32 CorrectableErrorMask; 722 UINT32 AdvancedErrorCapabilitiesAndControl; 723 UINT32 SecondaryUncorrectableErrorMask; 724 UINT32 SecondaryUncorrectableErrorSeverity; 725 UINT32 SecondaryAdvancedErrorCapabilitiesAndControl; 726 } 727 /// Generic Hardware Error Source Structure Definition 728 struct EFI_ACPI_4_0_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE 729 { 730 align(1): 731 UINT16 Type; 732 UINT16 SourceId; 733 UINT16 RelatedSourceId; 734 UINT8 Flags; 735 UINT8 Enabled; 736 UINT32 NumberOfRecordsToPreAllocate; 737 UINT32 MaxSectionsPerRecord; 738 UINT32 MaxRawDataLength; 739 EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress; 740 EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure; 741 UINT32 ErrorStatusBlockLength; 742 } 743 /// Generic Error Status Definition 744 struct EFI_ACPI_4_0_GENERIC_ERROR_STATUS_STRUCTURE 745 { 746 align(1): 747 EFI_ACPI_4_0_ERROR_BLOCK_STATUS BlockStatus; 748 UINT32 RawDataOffset; 749 UINT32 RawDataLength; 750 UINT32 DataLength; 751 UINT32 ErrorSeverity; 752 } 753 /// ERST - Error Record Serialization Table 754 struct EFI_ACPI_4_0_ERROR_RECORD_SERIALIZATION_TABLE_HEADER 755 { 756 align(1): 757 EFI_ACPI_DESCRIPTION_HEADER Header; 758 UINT32 SerializationHeaderSize; 759 UINT8[4] Reserved0; 760 UINT32 InstructionEntryCount; 761 } 762 /// ERST Version (as defined in ACPI 4.0 spec.) 763 enum EFI_ACPI_4_0_ERROR_RECORD_SERIALIZATION_TABLE_REVISION = 0x01; 764 /// ERST Serialization Actions 765 enum EFI_ACPI_4_0_ERST_BEGIN_WRITE_OPERATION = 0x00; 766 enum EFI_ACPI_4_0_ERST_BEGIN_READ_OPERATION = 0x01; 767 enum EFI_ACPI_4_0_ERST_BEGIN_CLEAR_OPERATION = 0x02; 768 enum EFI_ACPI_4_0_ERST_END_OPERATION = 0x03; 769 enum EFI_ACPI_4_0_ERST_SET_RECORD_OFFSET = 0x04; 770 enum EFI_ACPI_4_0_ERST_EXECUTE_OPERATION = 0x05; 771 enum EFI_ACPI_4_0_ERST_CHECK_BUSY_STATUS = 0x06; 772 enum EFI_ACPI_4_0_ERST_GET_COMMAND_STATUS = 0x07; 773 enum EFI_ACPI_4_0_ERST_GET_RECORD_IDENTIFIER = 0x08; 774 enum EFI_ACPI_4_0_ERST_SET_RECORD_IDENTIFIER = 0x09; 775 enum EFI_ACPI_4_0_ERST_GET_RECORD_COUNT = 0x0A; 776 enum EFI_ACPI_4_0_ERST_BEGIN_DUMMY_WRITE_OPERATION = 0x0B; 777 enum EFI_ACPI_4_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE = 0x0D; 778 enum EFI_ACPI_4_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH = 0x0E; 779 enum EFI_ACPI_4_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES = 0x0F; 780 /// ERST Action Command Status 781 //enum EFI_ACPI_4_0_EINJ_STATUS_SUCCESS = 0x00; 782 enum EFI_ACPI_4_0_EINJ_STATUS_NOT_ENOUGH_SPACE = 0x01; 783 enum EFI_ACPI_4_0_EINJ_STATUS_HARDWARE_NOT_AVAILABLE = 0x02; 784 enum EFI_ACPI_4_0_EINJ_STATUS_FAILED = 0x03; 785 enum EFI_ACPI_4_0_EINJ_STATUS_RECORD_STORE_EMPTY = 0x04; 786 enum EFI_ACPI_4_0_EINJ_STATUS_RECORD_NOT_FOUND = 0x05; 787 /// ERST Serialization Instructions 788 enum EFI_ACPI_4_0_ERST_READ_REGISTER = 0x00; 789 enum EFI_ACPI_4_0_ERST_READ_REGISTER_VALUE = 0x01; 790 enum EFI_ACPI_4_0_ERST_WRITE_REGISTER = 0x02; 791 enum EFI_ACPI_4_0_ERST_WRITE_REGISTER_VALUE = 0x03; 792 enum EFI_ACPI_4_0_ERST_NOOP = 0x04; 793 enum EFI_ACPI_4_0_ERST_LOAD_VAR1 = 0x05; 794 enum EFI_ACPI_4_0_ERST_LOAD_VAR2 = 0x06; 795 enum EFI_ACPI_4_0_ERST_STORE_VAR1 = 0x07; 796 enum EFI_ACPI_4_0_ERST_ADD = 0x08; 797 enum EFI_ACPI_4_0_ERST_SUBTRACT = 0x09; 798 enum EFI_ACPI_4_0_ERST_ADD_VALUE = 0x0A; 799 enum EFI_ACPI_4_0_ERST_SUBTRACT_VALUE = 0x0B; 800 enum EFI_ACPI_4_0_ERST_STALL = 0x0C; 801 enum EFI_ACPI_4_0_ERST_STALL_WHILE_TRUE = 0x0D; 802 enum EFI_ACPI_4_0_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE = 0x0E; 803 enum EFI_ACPI_4_0_ERST_GOTO = 0x0F; 804 enum EFI_ACPI_4_0_ERST_SET_SRC_ADDRESS_BASE = 0x10; 805 enum EFI_ACPI_4_0_ERST_SET_DST_ADDRESS_BASE = 0x11; 806 enum EFI_ACPI_4_0_ERST_MOVE_DATA = 0x12; 807 /// ERST Instruction Flags 808 enum EFI_ACPI_4_0_ERST_PRESERVE_REGISTER = 0x01; 809 /// ERST Serialization Instruction Entry 810 struct EFI_ACPI_4_0_ERST_SERIALIZATION_INSTRUCTION_ENTRY 811 { 812 align(1): 813 UINT8 SerializationAction; 814 UINT8 Instruction; 815 UINT8 Flags; 816 UINT8 Reserved0; 817 EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion; 818 UINT64 Value; 819 UINT64 Mask; 820 } 821 /// EINJ - Error Injection Table 822 struct EFI_ACPI_4_0_ERROR_INJECTION_TABLE_HEADER 823 { 824 align(1): 825 EFI_ACPI_DESCRIPTION_HEADER Header; 826 UINT32 InjectionHeaderSize; 827 UINT8 InjectionFlags; 828 UINT8[3] Reserved0; 829 UINT32 InjectionEntryCount; 830 } 831 /// EINJ Version (as defined in ACPI 4.0 spec.) 832 enum EFI_ACPI_4_0_ERROR_INJECTION_TABLE_REVISION = 0x01; 833 /// EINJ Error Injection Actions 834 enum EFI_ACPI_4_0_EINJ_BEGIN_INJECTION_OPERATION = 0x00; 835 enum EFI_ACPI_4_0_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE = 0x01; 836 enum EFI_ACPI_4_0_EINJ_SET_ERROR_TYPE = 0x02; 837 enum EFI_ACPI_4_0_EINJ_GET_ERROR_TYPE = 0x03; 838 enum EFI_ACPI_4_0_EINJ_END_OPERATION = 0x04; 839 enum EFI_ACPI_4_0_EINJ_EXECUTE_OPERATION = 0x05; 840 enum EFI_ACPI_4_0_EINJ_CHECK_BUSY_STATUS = 0x06; 841 enum EFI_ACPI_4_0_EINJ_GET_COMMAND_STATUS = 0x07; 842 enum EFI_ACPI_4_0_EINJ_TRIGGER_ERROR = 0xFF; 843 /// EINJ Action Command Status 844 enum EFI_ACPI_4_0_EINJ_STATUS_SUCCESS = 0x00; 845 enum EFI_ACPI_4_0_EINJ_STATUS_UNKNOWN_FAILURE = 0x01; 846 enum EFI_ACPI_4_0_EINJ_STATUS_INVALID_ACCESS = 0x02; 847 /// EINJ Error Type Definition 848 enum EFI_ACPI_4_0_EINJ_ERROR_PROCESSOR_CORRECTABLE = (1 << 0); 849 enum EFI_ACPI_4_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL = (1 << 1); 850 enum EFI_ACPI_4_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL = (1 << 2); 851 enum EFI_ACPI_4_0_EINJ_ERROR_MEMORY_CORRECTABLE = (1 << 3); 852 enum EFI_ACPI_4_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL = (1 << 4); 853 enum EFI_ACPI_4_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL = (1 << 5); 854 enum EFI_ACPI_4_0_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE = (1 << 6); 855 enum EFI_ACPI_4_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL = (1 << 7); 856 enum EFI_ACPI_4_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL = (1 << 8); 857 enum EFI_ACPI_4_0_EINJ_ERROR_PLATFORM_CORRECTABLE = (1 << 9); 858 enum EFI_ACPI_4_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL = (1 << 10); 859 enum EFI_ACPI_4_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL = (1 << 11); 860 /// EINJ Injection Instructions 861 enum EFI_ACPI_4_0_EINJ_READ_REGISTER = 0x00; 862 enum EFI_ACPI_4_0_EINJ_READ_REGISTER_VALUE = 0x01; 863 enum EFI_ACPI_4_0_EINJ_WRITE_REGISTER = 0x02; 864 enum EFI_ACPI_4_0_EINJ_WRITE_REGISTER_VALUE = 0x03; 865 enum EFI_ACPI_4_0_EINJ_NOOP = 0x04; 866 /// EINJ Instruction Flags 867 enum EFI_ACPI_4_0_EINJ_PRESERVE_REGISTER = 0x01; 868 /// EINJ Injection Instruction Entry 869 struct EFI_ACPI_4_0_EINJ_INJECTION_INSTRUCTION_ENTRY 870 { 871 align(1): 872 UINT8 InjectionAction; 873 UINT8 Instruction; 874 UINT8 Flags; 875 UINT8 Reserved0; 876 EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion; 877 UINT64 Value; 878 UINT64 Mask; 879 } 880 /// EINJ Trigger Action Table 881 struct EFI_ACPI_4_0_EINJ_TRIGGER_ACTION_TABLE 882 { 883 align(1): 884 UINT32 HeaderSize; 885 UINT32 Revision; 886 UINT32 TableSize; 887 UINT32 EntryCount; 888 } 889 /// "RSD PTR " Root System Description Pointer 890 enum EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE = SIGNATURE_64('R', 891 'S', 'D', ' ', 'P', 'T', 'R', ' '); 892 /// "APIC" Multiple APIC Description Table 893 enum EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE = SIGNATURE_32('A', 'P', 894 'I', 'C'); 895 /// "BERT" Boot Error Record Table 896 enum EFI_ACPI_4_0_BOOT_ERROR_RECORD_TABLE_SIGNATURE = SIGNATURE_32('B', 'E', 'R', 'T'); 897 /// "CPEP" Corrected Platform Error Polling Table 898 enum EFI_ACPI_4_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE = SIGNATURE_32( 899 'C', 'P', 'E', 'P'); 900 /// "DSDT" Differentiated System Description Table 901 enum EFI_ACPI_4_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE = SIGNATURE_32( 902 'D', 'S', 'D', 'T'); 903 /// "ECDT" Embedded Controller Boot Resources Table 904 enum EFI_ACPI_4_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE = SIGNATURE_32( 905 'E', 'C', 'D', 'T'); 906 /// "EINJ" Error Injection Table 907 enum EFI_ACPI_4_0_ERROR_INJECTION_TABLE_SIGNATURE = SIGNATURE_32('E', 'I', 'N', 'J'); 908 /// "ERST" Error Record Serialization Table 909 enum EFI_ACPI_4_0_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE = SIGNATURE_32('E', 'R', 910 'S', 'T'); 911 /// "FACP" Fixed ACPI Description Table 912 enum EFI_ACPI_4_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE = SIGNATURE_32('F', 'A', 'C', 913 'P'); 914 /// "FACS" Firmware ACPI Control Structure 915 enum EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE = SIGNATURE_32('F', 'A', 916 'C', 'S'); 917 /// "HEST" Hardware Error Source Table 918 enum EFI_ACPI_4_0_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE = SIGNATURE_32('H', 'E', 'S', 919 'T'); 920 /// "MSCT" Maximum System Characteristics Table 921 enum EFI_ACPI_4_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE = SIGNATURE_32('M', 922 'S', 'C', 'T'); 923 /// "PSDT" Persistent System Description Table 924 enum EFI_ACPI_4_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE = SIGNATURE_32('P', 925 'S', 'D', 'T'); 926 /// "RSDT" Root System Description Table 927 enum EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE = SIGNATURE_32('R', 'S', 928 'D', 'T'); 929 /// "SBST" Smart Battery Specification Table 930 enum EFI_ACPI_4_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE = SIGNATURE_32('S', 'B', 931 'S', 'T'); 932 /// "SLIT" System Locality Information Table 933 enum EFI_ACPI_4_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE = SIGNATURE_32('S', 'L', 934 'I', 'T'); 935 /// "SRAT" System Resource Affinity Table 936 enum EFI_ACPI_4_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE = SIGNATURE_32('S', 'R', 937 'A', 'T'); 938 /// "SSDT" Secondary System Description Table 939 enum EFI_ACPI_4_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE = SIGNATURE_32('S', 940 'S', 'D', 'T'); 941 /// "XSDT" Extended System Description Table 942 enum EFI_ACPI_4_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE = SIGNATURE_32('X', 'S', 943 'D', 'T'); 944 /// "BOOT" MS Simple Boot Spec 945 enum EFI_ACPI_4_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE = SIGNATURE_32('B', 'O', 'O', 'T'); 946 /// "DBGP" MS Debug Port Spec 947 enum EFI_ACPI_4_0_DEBUG_PORT_TABLE_SIGNATURE = SIGNATURE_32('D', 'B', 'G', 'P'); 948 /// "DMAR" DMA Remapping Table 949 enum EFI_ACPI_4_0_DMA_REMAPPING_TABLE_SIGNATURE = SIGNATURE_32('D', 'M', 'A', 'R'); 950 /// "ETDT" Event Timer Description Table 951 enum EFI_ACPI_4_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE = SIGNATURE_32('E', 'T', 952 'D', 'T'); 953 /// "HPET" IA-PC High Precision Event Timer Table 954 enum EFI_ACPI_4_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE = SIGNATURE_32('H', 'P', 955 'E', 'T'); 956 /// "iBFT" iSCSI Boot Firmware Table 957 enum EFI_ACPI_4_0_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE = SIGNATURE_32('i', 'B', 'F', 958 'T'); 959 /// "IVRS" I/O Virtualization Reporting Structure 960 enum EFI_ACPI_4_0_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE = SIGNATURE_32('I', 961 'V', 'R', 'S'); 962 /// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table 963 enum EFI_ACPI_4_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE = SIGNATURE_32( 964 'M', 'C', 'F', 'G'); 965 /// "MCHI" Management Controller Host Interface Table 966 enum EFI_ACPI_4_0_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE = SIGNATURE_32( 967 'M', 'C', 'H', 'I'); 968 /// "SPCR" Serial Port Concole Redirection Table 969 enum EFI_ACPI_4_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE = SIGNATURE_32('S', 970 'P', 'C', 'R'); 971 /// "SPMI" Server Platform Management Interface Table 972 enum EFI_ACPI_4_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE = SIGNATURE_32( 973 'S', 'P', 'M', 'I'); 974 /// "TCPA" Trusted Computing Platform Alliance Capabilities Table 975 enum EFI_ACPI_4_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE = SIGNATURE_32( 976 'T', 'C', 'P', 'A'); 977 /// "UEFI" UEFI ACPI Data Table 978 enum EFI_ACPI_4_0_UEFI_ACPI_DATA_TABLE_SIGNATURE = SIGNATURE_32('U', 'E', 'F', 'I'); 979 /// "WAET" Windows ACPI Enlightenment Table 980 enum EFI_ACPI_4_0_WINDOWS_ACPI_ENLIGHTENMENT_TABLE_SIGNATURE = SIGNATURE_32('W', 'A', 981 'E', 'T'); 982 /// "WDAT" Watchdog Action Table 983 enum EFI_ACPI_4_0_WATCHDOG_ACTION_TABLE_SIGNATURE = SIGNATURE_32('W', 'D', 'A', 'T'); 984 /// "WDRT" Watchdog Resource Table 985 enum EFI_ACPI_4_0_WATCHDOG_RESOURCE_TABLE_SIGNATURE = SIGNATURE_32('W', 'D', 'R', 'T');