1 /**
2 	Based on Uefi/UefiPxe.h, original notice:
3 
4 	This header file contains all of the PXE type definitions,
5 	structure prototypes, global variables and constants that
6 	are needed for porting PXE to EFI.
7 	
8 	Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
9 	This program and the accompanying materials are licensed and made available under
10 	the terms and conditions of the BSD License that accompanies this distribution.
11 	The full text of the license may be found at
12 	http://opensource.org/licenses/bsd-license.php.
13 	
14 	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15 	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 	
17 	@par Revision Reference:
18 	32/64-bit PXE specification:
19 	alpha-4, 99-Dec-17.
20 	
21 **/
22 module uefi.pxe;
23 import uefi.base;
24 import uefi.base_type;
25 
26 public:
27 extern (C):
28 // #define PXE_BUSTYPE(a, b, c, d) \
29 // ( \
30 // (((PXE_UINT32) (d) & 0xFF) << 24) | (((PXE_UINT32) (c) & 0xFF) << 16) | (((PXE_UINT32) (b) & 0xFF) << 8) | \
31 // ((PXE_UINT32) (a) & 0xFF) \
32 // )
33 UINT32 PXE_BUSTYPE(UINT32 a, UINT32 b, UINT32 c, UINT32 d)
34 {
35     return ((cast(PXE_UINT32)(d) & 0xFF) << 24) | ((cast(PXE_UINT32)(c) & 0xFF) << 16) | (
36         (cast(PXE_UINT32)(b) & 0xFF) << 8) | (cast(PXE_UINT32)(a) & 0xFF);
37 }
38 /// UNDI ROM ID and devive ID signature.
39 enum PXE_BUSTYPE_PXE = PXE_BUSTYPE('!', 'P', 'X', 'E');
40 /// BUS ROM ID signatures.
41 enum PXE_BUSTYPE_PCI = PXE_BUSTYPE('P', 'C', 'I', 'R');
42 enum PXE_BUSTYPE_PC_CARD = PXE_BUSTYPE('P', 'C', 'C', 'R');
43 enum PXE_BUSTYPE_USB = PXE_BUSTYPE('U', 'S', 'B', 'R');
44 enum PXE_BUSTYPE_1394 = PXE_BUSTYPE('1', '3', '9', '4');
45 // #define PXE_SWAP_UINT16(n)  ((((PXE_UINT16) (n) & 0x00FF) << 8) | (((PXE_UINT16) (n) & 0xFF00) >> 8))
46 // #define PXE_SWAP_UINT32(n) \
47 // ((((PXE_UINT32)(n) & 0x000000FF) << 24) | \
48 // (((PXE_UINT32)(n) & 0x0000FF00) << 8)  | \
49 // (((PXE_UINT32)(n) & 0x00FF0000) >> 8)  | \
50 // (((PXE_UINT32)(n) & 0xFF000000) >> 24))
51 // #define PXE_SWAP_UINT64(n) \
52 // ((((PXE_UINT64)(n) & 0x00000000000000FFULL) << 56) | \
53 // (((PXE_UINT64)(n) & 0x000000000000FF00ULL) << 40) | \
54 // (((PXE_UINT64)(n) & 0x0000000000FF0000ULL) << 24) | \
55 // (((PXE_UINT64)(n) & 0x00000000FF000000ULL) << 8)  | \
56 // (((PXE_UINT64)(n) & 0x000000FF00000000ULL) >> 8)  | \
57 // (((PXE_UINT64)(n) & 0x0000FF0000000000ULL) >> 24) | \
58 // (((PXE_UINT64)(n) & 0x00FF000000000000ULL) >> 40) | \
59 // (((PXE_UINT64)(n) & 0xFF00000000000000ULL) >> 56))
60 enum PXE_CPBSIZE_NOT_USED = 0; ///< zero 
61 enum PXE_DBSIZE_NOT_USED = 0; ///< zero 
62 enum PXE_CPBADDR_NOT_USED = cast(PXE_UINT64) 0; ///< zero 
63 enum PXE_DBADDR_NOT_USED = cast(PXE_UINT64) 0; ///< zero
64 alias PXE_VOID = VOID;
65 alias PXE_UINT8 = UINT8;
66 alias PXE_UINT16 = UINT16;
67 alias PXE_UINT32 = UINT32;
68 alias PXE_UINTN = UINTN;
69 /// Typedef unsigned long PXE_UINT64.
70 alias PXE_UINT64 = UINT64;
71 alias PXE_BOOL = PXE_UINT8;
72 enum PXE_FALSE = 0; ///< zero 
73 enum PXE_TRUE = (!PXE_FALSE);
74 alias PXE_OPCODE = PXE_UINT16;
75 /// Return UNDI operational state.
76 enum PXE_OPCODE_GET_STATE = 0x0000;
77 /// Change UNDI operational state from Stopped to Started.
78 enum PXE_OPCODE_START = 0x0001;
79 /// Change UNDI operational state from Started to Stopped.
80 enum PXE_OPCODE_STOP = 0x0002;
81 /// Get UNDI initialization information.
82 enum PXE_OPCODE_GET_INIT_INFO = 0x0003;
83 /// Get NIC configuration information.
84 enum PXE_OPCODE_GET_CONFIG_INFO = 0x0004;
85 /// Changed UNDI operational state from Started to Initialized.
86 enum PXE_OPCODE_INITIALIZE = 0x0005;
87 /// Re-initialize the NIC H/W.
88 enum PXE_OPCODE_RESET = 0x0006;
89 /// Change the UNDI operational state from Initialized to Started.
90 enum PXE_OPCODE_SHUTDOWN = 0x0007;
91 /// Read & change state of external interrupt enables.
92 enum PXE_OPCODE_INTERRUPT_ENABLES = 0x0008;
93 /// Read & change state of packet receive filters.
94 enum PXE_OPCODE_RECEIVE_FILTERS = 0x0009;
95 /// Read & change station MAC address.
96 enum PXE_OPCODE_STATION_ADDRESS = 0x000A;
97 /// Read traffic statistics.
98 enum PXE_OPCODE_STATISTICS = 0x000B;
99 /// Convert multicast IP address to multicast MAC address.
100 enum PXE_OPCODE_MCAST_IP_TO_MAC = 0x000C;
101 /// Read or change non-volatile storage on the NIC.
102 enum PXE_OPCODE_NVDATA = 0x000D;
103 /// Get & clear interrupt status.
104 enum PXE_OPCODE_GET_STATUS = 0x000E;
105 /// Fill media header in packet for transmit.
106 enum PXE_OPCODE_FILL_HEADER = 0x000F;
107 /// Transmit packet(s).
108 enum PXE_OPCODE_TRANSMIT = 0x0010;
109 /// Receive packet.
110 enum PXE_OPCODE_RECEIVE = 0x0011;
111 /// Last valid PXE UNDI OpCode number.
112 enum PXE_OPCODE_LAST_VALID = 0x0011;
113 alias PXE_OPFLAGS = PXE_UINT16;
114 enum PXE_OPFLAGS_NOT_USED = 0x0000;
115 ////////////////////////////////////////
116 ////////////////////////////////////////
117 ////////////////////////////////////////
118 ////////////////////////////////////////
119 /// UNDI Initialize
120 enum PXE_OPFLAGS_INITIALIZE_CABLE_DETECT_MASK = 0x0001;
121 enum PXE_OPFLAGS_INITIALIZE_DETECT_CABLE = 0x0000;
122 enum PXE_OPFLAGS_INITIALIZE_DO_NOT_DETECT_CABLE = 0x0001;
123 /// UNDI Reset
124 enum PXE_OPFLAGS_RESET_DISABLE_INTERRUPTS = 0x0001;
125 enum PXE_OPFLAGS_RESET_DISABLE_FILTERS = 0x0002;
126 /// UNDI Shutdown.
127 /// No OpFlags.
128 /// UNDI Interrupt Enables.
129 /// Select whether to enable or disable external interrupt signals.
130 /// Setting both enable and disable will return PXE_STATCODE_INVALID_OPFLAGS.
131 enum PXE_OPFLAGS_INTERRUPT_OPMASK = 0xC000;
132 enum PXE_OPFLAGS_INTERRUPT_ENABLE = 0x8000;
133 enum PXE_OPFLAGS_INTERRUPT_DISABLE = 0x4000;
134 enum PXE_OPFLAGS_INTERRUPT_READ = 0x0000;
135 /// Enable receive interrupts.  An external interrupt will be generated
136 /// after a complete non-error packet has been received.
137 enum PXE_OPFLAGS_INTERRUPT_RECEIVE = 0x0001;
138 /// Enable transmit interrupts.  An external interrupt will be generated
139 /// after a complete non-error packet has been transmitted.
140 enum PXE_OPFLAGS_INTERRUPT_TRANSMIT = 0x0002;
141 /// Enable command interrupts.  An external interrupt will be generated
142 /// when command execution stops.
143 enum PXE_OPFLAGS_INTERRUPT_COMMAND = 0x0004;
144 /// Generate software interrupt.  Setting this bit generates an external
145 /// interrupt, if it is supported by the hardware.
146 enum PXE_OPFLAGS_INTERRUPT_SOFTWARE = 0x0008;
147 /// UNDI Receive Filters.
148 /// Select whether to enable or disable receive filters.
149 /// Setting both enable and disable will return PXE_STATCODE_INVALID_OPCODE.
150 enum PXE_OPFLAGS_RECEIVE_FILTER_OPMASK = 0xC000;
151 enum PXE_OPFLAGS_RECEIVE_FILTER_ENABLE = 0x8000;
152 enum PXE_OPFLAGS_RECEIVE_FILTER_DISABLE = 0x4000;
153 enum PXE_OPFLAGS_RECEIVE_FILTER_READ = 0x0000;
154 /// To reset the contents of the multicast MAC address filter list,
155 /// set this OpFlag:
156 enum PXE_OPFLAGS_RECEIVE_FILTER_RESET_MCAST_LIST = 0x2000;
157 /// Enable unicast packet receiving.  Packets sent to the current station
158 /// MAC address will be received.
159 enum PXE_OPFLAGS_RECEIVE_FILTER_UNICAST = 0x0001;
160 /// Enable broadcast packet receiving.  Packets sent to the broadcast
161 /// MAC address will be received.
162 enum PXE_OPFLAGS_RECEIVE_FILTER_BROADCAST = 0x0002;
163 /// Enable filtered multicast packet receiving.  Packets sent to any
164 /// of the multicast MAC addresses in the multicast MAC address filter
165 /// list will be received.  If the filter list is empty, no multicast
166 enum PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST = 0x0004;
167 /// Enable promiscuous packet receiving.  All packets will be received.
168 enum PXE_OPFLAGS_RECEIVE_FILTER_PROMISCUOUS = 0x0008;
169 /// Enable promiscuous multicast packet receiving.  All multicast
170 /// packets will be received.
171 enum PXE_OPFLAGS_RECEIVE_FILTER_ALL_MULTICAST = 0x0010;
172 /// UNDI Station Address.
173 enum PXE_OPFLAGS_STATION_ADDRESS_READ = 0x0000;
174 enum PXE_OPFLAGS_STATION_ADDRESS_WRITE = 0x0000;
175 enum PXE_OPFLAGS_STATION_ADDRESS_RESET = 0x0001;
176 /// UNDI Statistics.
177 enum PXE_OPFLAGS_STATISTICS_READ = 0x0000;
178 enum PXE_OPFLAGS_STATISTICS_RESET = 0x0001;
179 /// UNDI MCast IP to MAC.
180 /// Identify the type of IP address in the CPB.
181 enum PXE_OPFLAGS_MCAST_IP_TO_MAC_OPMASK = 0x0003;
182 enum PXE_OPFLAGS_MCAST_IPV4_TO_MAC = 0x0000;
183 enum PXE_OPFLAGS_MCAST_IPV6_TO_MAC = 0x0001;
184 /// UNDI NvData.
185 /// Select the type of non-volatile data operation.
186 enum PXE_OPFLAGS_NVDATA_OPMASK = 0x0001;
187 enum PXE_OPFLAGS_NVDATA_READ = 0x0000;
188 enum PXE_OPFLAGS_NVDATA_WRITE = 0x0001;
189 /// UNDI Get Status.
190 /// Return current interrupt status.  This will also clear any interrupts
191 /// that are currently set.  This can be used in a polling routine.  The
192 /// interrupt flags are still set and cleared even when the interrupts
193 /// are disabled.
194 enum PXE_OPFLAGS_GET_INTERRUPT_STATUS = 0x0001;
195 /// Return list of transmitted buffers for recycling.  Transmit buffers
196 /// must not be changed or unallocated until they have recycled.  After
197 /// issuing a transmit command, wait for a transmit complete interrupt.
198 /// When a transmit complete interrupt is received, read the transmitted
199 /// buffers.  Do not plan on getting one buffer per interrupt.  Some
200 /// NICs and UNDIs may transmit multiple buffers per interrupt.
201 enum PXE_OPFLAGS_GET_TRANSMITTED_BUFFERS = 0x0002;
202 /// Return current media status.
203 enum PXE_OPFLAGS_GET_MEDIA_STATUS = 0x0004;
204 /// UNDI Fill Header.
205 enum PXE_OPFLAGS_FILL_HEADER_OPMASK = 0x0001;
206 enum PXE_OPFLAGS_FILL_HEADER_FRAGMENTED = 0x0001;
207 enum PXE_OPFLAGS_FILL_HEADER_WHOLE = 0x0000;
208 /// UNDI Transmit.
209 /// S/W UNDI only.  Return after the packet has been transmitted.  A
210 /// transmit complete interrupt will still be generated and the transmit
211 /// buffer will have to be recycled.
212 enum PXE_OPFLAGS_SWUNDI_TRANSMIT_OPMASK = 0x0001;
213 enum PXE_OPFLAGS_TRANSMIT_BLOCK = 0x0001;
214 enum PXE_OPFLAGS_TRANSMIT_DONT_BLOCK = 0x0000;
215 enum PXE_OPFLAGS_TRANSMIT_OPMASK = 0x0002;
216 enum PXE_OPFLAGS_TRANSMIT_FRAGMENTED = 0x0002;
217 enum PXE_OPFLAGS_TRANSMIT_WHOLE = 0x0000;
218 /// UNDI Receive.
219 /// No OpFlags.
220 /// PXE STATFLAGS.
221 alias PXE_STATFLAGS = PXE_UINT16;
222 enum PXE_STATFLAGS_INITIALIZE = 0x0000;
223 /// Common StatFlags that can be returned by all commands.
224 /// The COMMAND_COMPLETE and COMMAND_FAILED status flags must be
225 /// implemented by all UNDIs.  COMMAND_QUEUED is only needed by UNDIs
226 /// that support command queuing.
227 enum PXE_STATFLAGS_STATUS_MASK = 0xC000;
228 enum PXE_STATFLAGS_COMMAND_COMPLETE = 0xC000;
229 enum PXE_STATFLAGS_COMMAND_FAILED = 0x8000;
230 enum PXE_STATFLAGS_COMMAND_QUEUED = 0x4000;
231 /// UNDI Get State.
232 enum PXE_STATFLAGS_GET_STATE_MASK = 0x0003;
233 enum PXE_STATFLAGS_GET_STATE_INITIALIZED = 0x0002;
234 enum PXE_STATFLAGS_GET_STATE_STARTED = 0x0001;
235 enum PXE_STATFLAGS_GET_STATE_STOPPED = 0x0000;
236 /// UNDI Start.
237 /// No additional StatFlags.
238 /// UNDI Get Init Info.
239 enum PXE_STATFLAGS_CABLE_DETECT_MASK = 0x0001;
240 enum PXE_STATFLAGS_CABLE_DETECT_NOT_SUPPORTED = 0x0000;
241 enum PXE_STATFLAGS_CABLE_DETECT_SUPPORTED = 0x0001;
242 enum PXE_STATFLAGS_GET_STATUS_NO_MEDIA_MASK = 0x0002;
243 enum PXE_STATFLAGS_GET_STATUS_NO_MEDIA_NOT_SUPPORTED = 0x0000;
244 enum PXE_STATFLAGS_GET_STATUS_NO_MEDIA_SUPPORTED = 0x0002;
245 /// UNDI Initialize.
246 enum PXE_STATFLAGS_INITIALIZED_NO_MEDIA = 0x0001;
247 /// UNDI Reset.
248 enum PXE_STATFLAGS_RESET_NO_MEDIA = 0x0001;
249 /// UNDI Shutdown.
250 /// No additional StatFlags.
251 /// UNDI Interrupt Enables.
252 /// If set, receive interrupts are enabled.
253 enum PXE_STATFLAGS_INTERRUPT_RECEIVE = 0x0001;
254 /// If set, transmit interrupts are enabled.
255 enum PXE_STATFLAGS_INTERRUPT_TRANSMIT = 0x0002;
256 /// If set, command interrupts are enabled.
257 enum PXE_STATFLAGS_INTERRUPT_COMMAND = 0x0004;
258 /// UNDI Receive Filters.
259 /// If set, unicast packets will be received.
260 enum PXE_STATFLAGS_RECEIVE_FILTER_UNICAST = 0x0001;
261 /// If set, broadcast packets will be received.
262 enum PXE_STATFLAGS_RECEIVE_FILTER_BROADCAST = 0x0002;
263 /// If set, multicast packets that match up with the multicast address
264 /// filter list will be received.
265 enum PXE_STATFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST = 0x0004;
266 /// If set, all packets will be received.
267 enum PXE_STATFLAGS_RECEIVE_FILTER_PROMISCUOUS = 0x0008;
268 /// If set, all multicast packets will be received.
269 enum PXE_STATFLAGS_RECEIVE_FILTER_ALL_MULTICAST = 0x0010;
270 /// UNDI Station Address.
271 /// No additional StatFlags.
272 /// UNDI Statistics.
273 /// No additional StatFlags.
274 //// UNDI MCast IP to MAC.
275 ////
276 //// No additional StatFlags.
277 /// UNDI NvData.
278 /// No additional StatFlags.
279 /// UNDI Get Status.
280 /// Use to determine if an interrupt has occurred.
281 enum PXE_STATFLAGS_GET_STATUS_INTERRUPT_MASK = 0x000F;
282 enum PXE_STATFLAGS_GET_STATUS_NO_INTERRUPTS = 0x0000;
283 /// If set, at least one receive interrupt occurred.
284 enum PXE_STATFLAGS_GET_STATUS_RECEIVE = 0x0001;
285 /// If set, at least one transmit interrupt occurred.
286 enum PXE_STATFLAGS_GET_STATUS_TRANSMIT = 0x0002;
287 /// If set, at least one command interrupt occurred.
288 enum PXE_STATFLAGS_GET_STATUS_COMMAND = 0x0004;
289 /// If set, at least one software interrupt occurred.
290 enum PXE_STATFLAGS_GET_STATUS_SOFTWARE = 0x0008;
291 /// This flag is set if the transmitted buffer queue is empty.  This flag
292 /// will be set if all transmitted buffer addresses get written into the DB.
293 enum PXE_STATFLAGS_GET_STATUS_TXBUF_QUEUE_EMPTY = 0x0010;
294 /// This flag is set if no transmitted buffer addresses were written
295 /// into the DB.  (This could be because DBsize was too small.)
296 enum PXE_STATFLAGS_GET_STATUS_NO_TXBUFS_WRITTEN = 0x0020;
297 /// This flag is set if there is no media detected.
298 enum PXE_STATFLAGS_GET_STATUS_NO_MEDIA = 0x0040;
299 /// UNDI Fill Header.
300 /// No additional StatFlags.
301 /// UNDI Transmit.
302 /// No additional StatFlags.
303 /// UNDI Receive
304 ///.
305 /// No additional StatFlags.
306 alias PXE_STATCODE = PXE_UINT16;
307 enum PXE_STATCODE_INITIALIZE = 0x0000;
308 /// Common StatCodes returned by all UNDI commands, UNDI protocol functions
309 /// and BC protocol functions.
310 enum PXE_STATCODE_SUCCESS = 0x0000;
311 enum PXE_STATCODE_INVALID_CDB = 0x0001;
312 enum PXE_STATCODE_INVALID_CPB = 0x0002;
313 enum PXE_STATCODE_BUSY = 0x0003;
314 enum PXE_STATCODE_QUEUE_FUL = 0x0004;
315 enum PXE_STATCODE_ALREADY_STARTED = 0x0005;
316 enum PXE_STATCODE_NOT_STARTED = 0x0006;
317 enum PXE_STATCODE_NOT_SHUTDOWN = 0x0007;
318 enum PXE_STATCODE_ALREADY_INITIALIZED = 0x0008;
319 enum PXE_STATCODE_NOT_INITIALIZED = 0x0009;
320 enum PXE_STATCODE_DEVICE_FAILURE = 0x000A;
321 enum PXE_STATCODE_NVDATA_FAILURE = 0x000B;
322 enum PXE_STATCODE_UNSUPPORTED = 0x000C;
323 enum PXE_STATCODE_BUFFER_FUL = 0x000D;
324 enum PXE_STATCODE_INVALID_PARAMETER = 0x000E;
325 enum PXE_STATCODE_INVALID_UNDI = 0x000F;
326 enum PXE_STATCODE_IPV4_NOT_SUPPORTED = 0x0010;
327 enum PXE_STATCODE_IPV6_NOT_SUPPORTED = 0x0011;
328 enum PXE_STATCODE_NOT_ENOUGH_MEMORY = 0x0012;
329 enum PXE_STATCODE_NO_DATA = 0x0013;
330 alias PXE_IFNUM = PXE_UINT16;
331 /// This interface number must be passed to the S/W UNDI Start command.
332 enum PXE_IFNUM_START = 0x0000;
333 /// This interface number is returned by the S/W UNDI Get State and
334 /// Start commands if information in the CDB, CPB or DB is invalid.
335 enum PXE_IFNUM_INVALID = 0x0000;
336 alias PXE_CONTROL = PXE_UINT16;
337 /// Setting this flag directs the UNDI to queue this command for later
338 /// execution if the UNDI is busy and it supports command queuing.
339 /// If queuing is not supported, a PXE_STATCODE_INVALID_CONTROL error
340 /// is returned.  If the queue is full, a PXE_STATCODE_CDB_QUEUE_FULL
341 /// error is returned.
342 enum PXE_CONTROL_QUEUE_IF_BUSY = 0x0002;
343 /// These two bit values are used to determine if there are more UNDI
344 /// CDB structures following this one.  If the link bit is set, there
345 /// must be a CDB structure following this one.  Execution will start
346 /// on the next CDB structure as soon as this one completes successfully.
347 /// If an error is generated by this command, execution will stop.
348 enum PXE_CONTROL_LINK = 0x0001;
349 enum PXE_CONTROL_LAST_CDB_IN_LIST = 0x0000;
350 alias PXE_FRAME_TYPE = PXE_UINT8;
351 enum PXE_FRAME_TYPE_NONE = 0x00;
352 enum PXE_FRAME_TYPE_UNICAST = 0x01;
353 enum PXE_FRAME_TYPE_BROADCAST = 0x02;
354 enum PXE_FRAME_TYPE_FILTERED_MULTICAST = 0x03;
355 enum PXE_FRAME_TYPE_PROMISCUOUS = 0x04;
356 enum PXE_FRAME_TYPE_PROMISCUOUS_MULTICAST = 0x05;
357 enum PXE_FRAME_TYPE_MULTICAST = PXE_FRAME_TYPE_FILTERED_MULTICAST;
358 alias PXE_IPV4 = PXE_UINT32;
359 alias PXE_IPV6 = PXE_UINT32[4];
360 enum PXE_MAC_LENGTH = 32;
361 alias PXE_MAC_ADDR = PXE_UINT8[PXE_MAC_LENGTH];
362 alias PXE_IFTYPE = PXE_UINT8;
363 alias PXE_MEDIA_PROTOCOL = UINT16;
364 /// This information is from the ARP section of RFC 1700.
365 ///     1 Ethernet (10Mb)                                    [JBP]
366 ///     2 Experimental Ethernet (3Mb)                        [JBP]
367 ///     3 Amateur Radio AX.25                                [PXK]
368 ///     4 Proteon ProNET Token Ring                          [JBP]
369 ///     5 Chaos                                              [GXP]
370 ///     6 IEEE 802 Networks                                  [JBP]
371 ///     7 ARCNET                                             [JBP]
372 ///     8 Hyperchannel                                       [JBP]
373 ///     9 Lanstar                                             [TU]
374 ///    10 Autonet Short Address                             [MXB1]
375 ///    11 LocalTalk                                         [JKR1]
376 ///    12 LocalNet (IBM* PCNet or SYTEK* LocalNET)           [JXM]
377 ///    13 Ultra link                                        [RXD2]
378 ///    14 SMDS                                              [GXC1]
379 ///    15 Frame Relay                                        [AGM]
380 ///    16 Asynchronous Transmission Mode (ATM)              [JXB2]
381 ///    17 HDLC                                               [JBP]
382 ///    18 Fibre Channel                            [Yakov Rekhter]
383 ///    19 Asynchronous Transmission Mode (ATM)      [Mark Laubach]
384 ///    20 Serial Line                                        [JBP]
385 ///    21 Asynchronous Transmission Mode (ATM)              [MXB1]
386 /// * Other names and brands may be claimed as the property of others.
387 enum PXE_IFTYPE_ETHERNET = 0x01;
388 enum PXE_IFTYPE_TOKENRING = 0x04;
389 enum PXE_IFTYPE_FIBRE_CHANNEL = 0x12;
390 struct PXE_HW_UNDI
391 {
392 align(1):
393     PXE_UINT32 Signature; ///< PXE_ROMID_SIGNATURE.
394     PXE_UINT8 Len; ///< sizeof(PXE_HW_UNDI).
395     PXE_UINT8 Fudge; ///< makes 8-bit cksum equal zero.
396     PXE_UINT8 Rev; ///< PXE_ROMID_REV.
397     PXE_UINT8 IFcnt; ///< physical connector count lower byte.
398     PXE_UINT8 MajorVer; ///< PXE_ROMID_MAJORVER.
399     PXE_UINT8 MinorVer; ///< PXE_ROMID_MINORVER.
400     PXE_UINT8 IFcntExt; ///< physical connector count upper byte.
401     PXE_UINT8 reserved; ///< zero, not used.
402     PXE_UINT32 Implementation; ///< implementation flags.
403     ///< reserved             ///< vendor use.
404     ///< UINT32 Status;       ///< status port.
405     ///< UINT32 Command;      ///< command port.
406     ///< UINT64 CDBaddr;      ///< CDB address port.
407     ///<
408 }
409 /// Status port bit definitions.
410 /// UNDI operation state.
411 enum PXE_HWSTAT_STATE_MASK = 0xC0000000;
412 enum PXE_HWSTAT_BUSY = 0xC0000000;
413 enum PXE_HWSTAT_INITIALIZED = 0x80000000;
414 enum PXE_HWSTAT_STARTED = 0x40000000;
415 enum PXE_HWSTAT_STOPPED = 0x00000000;
416 /// If set, last command failed.
417 enum PXE_HWSTAT_COMMAND_FAILED = 0x20000000;
418 /// If set, identifies enabled receive filters.
419 enum PXE_HWSTAT_PROMISCUOUS_MULTICAST_RX_ENABLED = 0x00001000;
420 enum PXE_HWSTAT_PROMISCUOUS_RX_ENABLED = 0x00000800;
421 enum PXE_HWSTAT_BROADCAST_RX_ENABLED = 0x00000400;
422 enum PXE_HWSTAT_MULTICAST_RX_ENABLED = 0x00000200;
423 enum PXE_HWSTAT_UNICAST_RX_ENABLED = 0x00000100;
424 /// If set, identifies enabled external interrupts.
425 enum PXE_HWSTAT_SOFTWARE_INT_ENABLED = 0x00000080;
426 enum PXE_HWSTAT_TX_COMPLETE_INT_ENABLED = 0x00000040;
427 enum PXE_HWSTAT_PACKET_RX_INT_ENABLED = 0x00000020;
428 enum PXE_HWSTAT_CMD_COMPLETE_INT_ENABLED = 0x00000010;
429 /// If set, identifies pending interrupts.
430 enum PXE_HWSTAT_SOFTWARE_INT_PENDING = 0x00000008;
431 enum PXE_HWSTAT_TX_COMPLETE_INT_PENDING = 0x00000004;
432 enum PXE_HWSTAT_PACKET_RX_INT_PENDING = 0x00000002;
433 enum PXE_HWSTAT_CMD_COMPLETE_INT_PENDING = 0x00000001;
434 /// Command port definitions.
435 /// If set, CDB identified in CDBaddr port is given to UNDI.
436 /// If not set, other bits in this word will be processed.
437 enum PXE_HWCMD_ISSUE_COMMAND = 0x80000000;
438 enum PXE_HWCMD_INTS_AND_FILTS = 0x00000000;
439 /// Use these to enable/disable receive filters.
440 enum PXE_HWCMD_PROMISCUOUS_MULTICAST_RX_ENABLE = 0x00001000;
441 enum PXE_HWCMD_PROMISCUOUS_RX_ENABLE = 0x00000800;
442 enum PXE_HWCMD_BROADCAST_RX_ENABLE = 0x00000400;
443 enum PXE_HWCMD_MULTICAST_RX_ENABLE = 0x00000200;
444 enum PXE_HWCMD_UNICAST_RX_ENABLE = 0x00000100;
445 /// Use these to enable/disable external interrupts.
446 enum PXE_HWCMD_SOFTWARE_INT_ENABLE = 0x00000080;
447 enum PXE_HWCMD_TX_COMPLETE_INT_ENABLE = 0x00000040;
448 enum PXE_HWCMD_PACKET_RX_INT_ENABLE = 0x00000020;
449 enum PXE_HWCMD_CMD_COMPLETE_INT_ENABLE = 0x00000010;
450 /// Use these to clear pending external interrupts.
451 enum PXE_HWCMD_CLEAR_SOFTWARE_INT = 0x00000008;
452 enum PXE_HWCMD_CLEAR_TX_COMPLETE_INT = 0x00000004;
453 enum PXE_HWCMD_CLEAR_PACKET_RX_INT = 0x00000002;
454 enum PXE_HWCMD_CLEAR_CMD_COMPLETE_INT = 0x00000001;
455 struct PXE_SW_UNDI
456 {
457 align(1):
458     PXE_UINT32 Signature; ///< PXE_ROMID_SIGNATURE.
459     PXE_UINT8 Len; ///< sizeof(PXE_SW_UNDI).
460     PXE_UINT8 Fudge; ///< makes 8-bit cksum zero.
461     PXE_UINT8 Rev; ///< PXE_ROMID_REV.
462     PXE_UINT8 IFcnt; ///< physical connector count lower byte.
463     PXE_UINT8 MajorVer; ///< PXE_ROMID_MAJORVER.
464     PXE_UINT8 MinorVer; ///< PXE_ROMID_MINORVER.
465     PXE_UINT8 IFcntExt; ///< physical connector count upper byte.
466     PXE_UINT8 reserved1; ///< zero, not used.
467     PXE_UINT32 Implementation; ///< Implementation flags.
468     PXE_UINT64 EntryPoint; ///< API entry point.
469     PXE_UINT8[3] reserved2; ///< zero, not used.
470     PXE_UINT8 BusCnt; ///< number of bustypes supported.
471     PXE_UINT32[1] BusType; ///< list of supported bustypes.
472 }
473 
474 union PXE_UNDI
475 {
476     PXE_HW_UNDI hw;
477     PXE_SW_UNDI sw;
478 }
479 /// Signature of !PXE structure.
480 enum PXE_ROMID_SIGNATURE = PXE_BUSTYPE('!', 'P', 'X', 'E');
481 /// !PXE structure format revision
482 ///.
483 enum PXE_ROMID_REV = 0x02;
484 /// UNDI command interface revision.  These are the values that get sent
485 /// in option 94 (Client Network Interface Identifier) in the DHCP Discover
486 /// and PXE Boot Server Request packets.
487 enum PXE_ROMID_MAJORVER = 0x03;
488 enum PXE_ROMID_MINORVER = 0x01;
489 /// Implementation flags.
490 enum PXE_ROMID_IMP_HW_UNDI = 0x80000000;
491 enum PXE_ROMID_IMP_SW_VIRT_ADDR = 0x40000000;
492 enum PXE_ROMID_IMP_64BIT_DEVICE = 0x00010000;
493 enum PXE_ROMID_IMP_FRAG_SUPPORTED = 0x00008000;
494 enum PXE_ROMID_IMP_CMD_LINK_SUPPORTED = 0x00004000;
495 enum PXE_ROMID_IMP_CMD_QUEUE_SUPPORTED = 0x00002000;
496 enum PXE_ROMID_IMP_MULTI_FRAME_SUPPORTED = 0x00001000;
497 enum PXE_ROMID_IMP_NVDATA_SUPPORT_MASK = 0x00000C00;
498 enum PXE_ROMID_IMP_NVDATA_BULK_WRITABLE = 0x00000C00;
499 enum PXE_ROMID_IMP_NVDATA_SPARSE_WRITABLE = 0x00000800;
500 enum PXE_ROMID_IMP_NVDATA_READ_ONLY = 0x00000400;
501 enum PXE_ROMID_IMP_NVDATA_NOT_AVAILABLE = 0x00000000;
502 enum PXE_ROMID_IMP_STATISTICS_SUPPORTED = 0x00000200;
503 enum PXE_ROMID_IMP_STATION_ADDR_SETTABLE = 0x00000100;
504 enum PXE_ROMID_IMP_PROMISCUOUS_MULTICAST_RX_SUPPORTED = 0x00000080;
505 enum PXE_ROMID_IMP_PROMISCUOUS_RX_SUPPORTED = 0x00000040;
506 enum PXE_ROMID_IMP_BROADCAST_RX_SUPPORTED = 0x00000020;
507 enum PXE_ROMID_IMP_FILTERED_MULTICAST_RX_SUPPORTED = 0x00000010;
508 enum PXE_ROMID_IMP_SOFTWARE_INT_SUPPORTED = 0x00000008;
509 enum PXE_ROMID_IMP_TX_COMPLETE_INT_SUPPORTED = 0x00000004;
510 enum PXE_ROMID_IMP_PACKET_RX_INT_SUPPORTED = 0x00000002;
511 enum PXE_ROMID_IMP_CMD_COMPLETE_INT_SUPPORTED = 0x00000001;
512 struct PXE_CDB
513 {
514 align(1):
515     PXE_OPCODE OpCode;
516     PXE_OPFLAGS OpFlags;
517     PXE_UINT16 CPBsize;
518     PXE_UINT16 DBsize;
519     PXE_UINT64 CPBaddr;
520     PXE_UINT64 DBaddr;
521     PXE_STATCODE StatCode;
522     PXE_STATFLAGS StatFlags;
523     PXE_UINT16 IFnum;
524     PXE_CONTROL Control;
525 }
526 
527 union PXE_IP_ADDR
528 {
529     PXE_IPV6 IPv6;
530     PXE_IPV4 IPv4;
531 }
532 
533 union PXE_DEVICE
534 {
535     ///
536     /// PCI and PC Card NICs are both identified using bus, device
537     /// and function numbers.  For PC Card, this may require PC
538     /// Card services to be loaded in the BIOS or preboot
539     /// environment.
540     ///
541     struct PCI
542     {
543         ///
544         /// See S/W UNDI ROMID structure definition for PCI and
545         /// PCC BusType definitions.
546         ///
547         PXE_UINT32 BusType;
548         ///
549         /// Bus, device & function numbers that locate this device.
550         ///
551         PXE_UINT16 Bus;
552         PXE_UINT8 Device;
553         PXE_UINT8 Function;
554     }
555 
556     UINT64 PCC;
557 }
558 /// cpb and db definitions
559 enum MAX_PCI_CONFIG_LEN = 64; ///< # of dwords. 
560 enum MAX_EEPROM_LEN = 128; ///< # of dwords. 
561 enum MAX_XMIT_BUFFERS = 32; ///< recycling Q length for xmit_done. 
562 enum MAX_MCAST_ADDRESS_CNT = 8;
563 struct PXE_CPB_START_30
564 {
565 align(1):
566     ///
567     /// PXE_VOID Delay(UINTN microseconds);
568     ///
569     /// UNDI will never request a delay smaller than 10 microseconds
570     /// and will always request delays in increments of 10 microseconds.
571     /// The Delay() CallBack routine must delay between n and n + 10
572     /// microseconds before returning control to the UNDI.
573     ///
574     /// This field cannot be set to zero.
575     ///
576     UINT64 Delay;
577     ///
578     /// PXE_VOID Block(UINT32 enable);
579     ///
580     /// UNDI may need to block multi-threaded/multi-processor access to
581     /// critical code sections when programming or accessing the network
582     /// device.  To this end, a blocking service is needed by the UNDI.
583     /// When UNDI needs a block, it will call Block() passing a non-zero
584     /// value.  When UNDI no longer needs a block, it will call Block()
585     /// with a zero value.  When called, if the Block() is already enabled,
586     /// do not return control to the UNDI until the previous Block() is
587     /// disabled.
588     ///
589     /// This field cannot be set to zero.
590     ///
591     UINT64 Block;
592     ///
593     /// PXE_VOID Virt2Phys(UINT64 virtual, UINT64 physical_ptr);
594     ///
595     /// UNDI will pass the virtual address of a buffer and the virtual
596     /// address of a 64-bit physical buffer.  Convert the virtual address
597     /// to a physical address and write the result to the physical address
598     /// buffer.  If virtual and physical addresses are the same, just
599     /// copy the virtual address to the physical address buffer.
600     ///
601     /// This field can be set to zero if virtual and physical addresses
602     /// are equal.
603     ///
604     UINT64 Virt2Phys;
605     ///
606     /// PXE_VOID Mem_IO(UINT8 read_write, UINT8 len, UINT64 port,
607     ///              UINT64 buf_addr);
608     ///
609     /// UNDI will read or write the device io space using this call back
610     /// function. It passes the number of bytes as the len parameter and it
611     /// will be either 1,2,4 or 8.
612     ///
613     /// This field can not be set to zero.
614     ///
615     UINT64 Mem_IO;
616 }
617 
618 struct PXE_CPB_START_31
619 {
620 align(1):
621     ///
622     /// PXE_VOID Delay(UINT64 UnqId, UINTN microseconds);
623     ///
624     /// UNDI will never request a delay smaller than 10 microseconds
625     /// and will always request delays in increments of 10 microseconds.
626     /// The Delay() CallBack routine must delay between n and n + 10
627     /// microseconds before returning control to the UNDI.
628     ///
629     /// This field cannot be set to zero.
630     ///
631     UINT64 Delay;
632     ///
633     /// PXE_VOID Block(UINT64 unq_id, UINT32 enable);
634     ///
635     /// UNDI may need to block multi-threaded/multi-processor access to
636     /// critical code sections when programming or accessing the network
637     /// device.  To this end, a blocking service is needed by the UNDI.
638     /// When UNDI needs a block, it will call Block() passing a non-zero
639     /// value.  When UNDI no longer needs a block, it will call Block()
640     /// with a zero value.  When called, if the Block() is already enabled,
641     /// do not return control to the UNDI until the previous Block() is
642     /// disabled.
643     ///
644     /// This field cannot be set to zero.
645     ///
646     UINT64 Block;
647     ///
648     /// PXE_VOID Virt2Phys(UINT64 UnqId, UINT64 virtual, UINT64 physical_ptr);
649     ///
650     /// UNDI will pass the virtual address of a buffer and the virtual
651     /// address of a 64-bit physical buffer.  Convert the virtual address
652     /// to a physical address and write the result to the physical address
653     /// buffer.  If virtual and physical addresses are the same, just
654     /// copy the virtual address to the physical address buffer.
655     ///
656     /// This field can be set to zero if virtual and physical addresses
657     /// are equal.
658     ///
659     UINT64 Virt2Phys;
660     ///
661     /// PXE_VOID Mem_IO(UINT64 UnqId, UINT8 read_write, UINT8 len, UINT64 port,
662     ///              UINT64 buf_addr);
663     ///
664     /// UNDI will read or write the device io space using this call back
665     /// function. It passes the number of bytes as the len parameter and it
666     /// will be either 1,2,4 or 8.
667     ///
668     /// This field can not be set to zero.
669     ///
670     UINT64 Mem_IO;
671     ///
672     /// PXE_VOID Map_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,
673     ///                 UINT32 Direction, UINT64 mapped_addr);
674     ///
675     /// UNDI will pass the virtual address of a buffer, direction of the data
676     /// flow from/to the mapped buffer (the constants are defined below)
677     /// and a place holder (pointer) for the mapped address.
678     /// This call will Map the given address to a physical DMA address and write
679     /// the result to the mapped_addr pointer.  If there is no need to
680     /// map the given address to a lower address (i.e. the given address is
681     /// associated with a physical address that is already compatible to be
682     /// used with the DMA, it converts the given virtual address to it's
683     /// physical address and write that in the mapped address pointer.
684     ///
685     /// This field can be set to zero if there is no mapping service available.
686     ///
687     UINT64 Map_Mem;
688     ///
689     /// PXE_VOID UnMap_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,
690     ///            UINT32 Direction, UINT64 mapped_addr);
691     ///
692     /// UNDI will pass the virtual and mapped addresses of a buffer.
693     /// This call will un map the given address.
694     ///
695     /// This field can be set to zero if there is no unmapping service available.
696     ///
697     UINT64 UnMap_Mem;
698     ///
699     /// PXE_VOID Sync_Mem(UINT64 unq_id, UINT64 virtual,
700     ///            UINT32 size, UINT32 Direction, UINT64 mapped_addr);
701     ///
702     /// UNDI will pass the virtual and mapped addresses of a buffer.
703     /// This call will synchronize the contents of both the virtual and mapped.
704     /// buffers for the given Direction.
705     ///
706     /// This field can be set to zero if there is no service available.
707     ///
708     UINT64 Sync_Mem;
709     ///
710     /// protocol driver can provide anything for this Unique_ID, UNDI remembers
711     /// that as just a 64bit value assocaited to the interface specified by
712     /// the ifnum and gives it back as a parameter to all the call-back routines
713     /// when calling for that interface!
714     ///
715     UINT64 Unique_ID;
716 }
717 
718 enum TO_AND_FROM_DEVICE = 0;
719 enum FROM_DEVICE = 1;
720 enum TO_DEVICE = 2;
721 enum PXE_DELAY_MILLISECOND = 1000;
722 enum PXE_DELAY_SECOND = 1000000;
723 enum PXE_IO_READ = 0;
724 enum PXE_IO_WRITE = 1;
725 enum PXE_MEM_READ = 2;
726 enum PXE_MEM_WRITE = 4;
727 struct PXE_DB_GET_INIT_INFO
728 {
729 align(1):
730     ///
731     /// Minimum length of locked memory buffer that must be given to
732     /// the Initialize command. Giving UNDI more memory will generally
733     /// give better performance.
734     ///
735     /// If MemoryRequired is zero, the UNDI does not need and will not
736     /// use system memory to receive and transmit packets.
737     ///
738     PXE_UINT32 MemoryRequired;
739     ///
740     /// Maximum frame data length for Tx/Rx excluding the media header.
741     ///
742     PXE_UINT32 FrameDataLen;
743     ///
744     /// Supported link speeds are in units of mega bits.  Common ethernet
745     /// values are 10, 100 and 1000.  Unused LinkSpeeds[] entries are zero
746     /// filled.
747     ///
748     PXE_UINT32[4] LinkSpeeds;
749     ///
750     /// Number of non-volatile storage items.
751     ///
752     PXE_UINT32 NvCount;
753     ///
754     /// Width of non-volatile storage item in bytes.  0, 1, 2 or 4
755     ///
756     PXE_UINT16 NvWidth;
757     ///
758     /// Media header length.  This is the typical media header length for
759     /// this UNDI.  This information is needed when allocating receive
760     /// and transmit buffers.
761     ///
762     PXE_UINT16 MediaHeaderLen;
763     ///
764     /// Number of bytes in the NIC hardware (MAC) address.
765     ///
766     PXE_UINT16 HWaddrLen;
767     ///
768     /// Maximum number of multicast MAC addresses in the multicast
769     /// MAC address filter list.
770     ///
771     PXE_UINT16 MCastFilterCnt;
772     ///
773     /// Default number and size of transmit and receive buffers that will
774     /// be allocated by the UNDI.  If MemoryRequired is non-zero, this
775     /// allocation will come out of the memory buffer given to the Initialize
776     /// command.  If MemoryRequired is zero, this allocation will come out of
777     /// memory on the NIC.
778     ///
779     PXE_UINT16 TxBufCnt;
780     PXE_UINT16 TxBufSize;
781     PXE_UINT16 RxBufCnt;
782     PXE_UINT16 RxBufSize;
783     ///
784     /// Hardware interface types defined in the Assigned Numbers RFC
785     /// and used in DHCP and ARP packets.
786     /// See the PXE_IFTYPE typedef and PXE_IFTYPE_xxx macros.
787     ///
788     PXE_UINT8 IFtype;
789     ///
790     /// Supported duplex.  See PXE_DUPLEX_xxxxx #defines below.
791     ///
792     PXE_UINT8 SupportedDuplexModes;
793     ///
794     /// Supported loopback options.  See PXE_LOOPBACK_xxxxx #defines below.
795     ///
796     PXE_UINT8 SupportedLoopBackModes;
797 }
798 
799 enum PXE_MAX_TXRX_UNIT_ETHER = 1500;
800 enum PXE_HWADDR_LEN_ETHER = 0x0006;
801 enum PXE_MAC_HEADER_LEN_ETHER = 0x000E;
802 enum PXE_DUPLEX_ENABLE_FUL_SUPPORTED = 1;
803 enum PXE_DUPLEX_FORCE_FUL_SUPPORTED = 2;
804 enum PXE_LOOPBACK_INTERNAL_SUPPORTED = 1;
805 enum PXE_LOOPBACK_EXTERNAL_SUPPORTED = 2;
806 struct PXE_PCI_CONFIG_INFO
807 {
808 align(1):
809     ///
810     /// This is the flag field for the PXE_DB_GET_CONFIG_INFO union.
811     /// For PCI bus devices, this field is set to PXE_BUSTYPE_PCI.
812     ///
813     UINT32 BusType;
814     ///
815     /// This identifies the PCI network device that this UNDI interface.
816     /// is bound to.
817     ///
818     UINT16 Bus;
819     UINT8 Device;
820     UINT8 Function;
821     ///
822     /// This is a copy of the PCI configuration space for this
823     /// network device.
824     ///
825     union Config
826     {
827         UINT8[256] Byte;
828         UINT16[128] Word;
829         UINT32[64] Dword;
830     }
831 }
832 
833 struct PXE_PCC_CONFIG_INFO
834 {
835 align(1):
836     ///
837     /// This is the flag field for the PXE_DB_GET_CONFIG_INFO union.
838     /// For PCC bus devices, this field is set to PXE_BUSTYPE_PCC.
839     ///
840     PXE_UINT32 BusType;
841     ///
842     /// This identifies the PCC network device that this UNDI interface
843     /// is bound to.
844     ///
845     PXE_UINT16 Bus;
846     PXE_UINT8 Device;
847     PXE_UINT8 Function;
848     ///
849     /// This is a copy of the PCC configuration space for this
850     /// network device.
851     ///
852     union Config
853     {
854         PXE_UINT8[256] Byte;
855         PXE_UINT16[128] Word;
856         PXE_UINT32[64] Dword;
857     }
858 }
859 
860 union PXE_DB_GET_CONFIG_INFO
861 {
862     PXE_PCI_CONFIG_INFO pci;
863     PXE_PCC_CONFIG_INFO pcc;
864 }
865 
866 struct PXE_CPB_INITIALIZE
867 {
868 align(1):
869     ///
870     /// Address of first (lowest) byte of the memory buffer.  This buffer must
871     /// be in contiguous physical memory and cannot be swapped out.  The UNDI
872     /// will be using this for transmit and receive buffering.
873     ///
874     PXE_UINT64 MemoryAddr;
875     ///
876     /// MemoryLength must be greater than or equal to MemoryRequired
877     /// returned by the Get Init Info command.
878     ///
879     PXE_UINT32 MemoryLength;
880     ///
881     /// Desired link speed in Mbit/sec.  Common ethernet values are 10, 100
882     /// and 1000.  Setting a value of zero will auto-detect and/or use the
883     /// default link speed (operation depends on UNDI/NIC functionality).
884     ///
885     PXE_UINT32 LinkSpeed;
886     ///
887     /// Suggested number and size of receive and transmit buffers to
888     /// allocate.  If MemoryAddr and MemoryLength are non-zero, this
889     /// allocation comes out of the supplied memory buffer.  If MemoryAddr
890     /// and MemoryLength are zero, this allocation comes out of memory
891     /// on the NIC.
892     ///
893     /// If these fields are set to zero, the UNDI will allocate buffer
894     /// counts and sizes as it sees fit.
895     ///
896     PXE_UINT16 TxBufCnt;
897     PXE_UINT16 TxBufSize;
898     PXE_UINT16 RxBufCnt;
899     PXE_UINT16 RxBufSize;
900     ///
901     /// The following configuration parameters are optional and must be zero
902     /// to use the default values.
903     ///
904     PXE_UINT8 DuplexMode;
905     PXE_UINT8 LoopBackMode;
906 }
907 
908 enum PXE_DUPLEX_DEFAULT = 0x00;
909 enum PXE_FORCE_FUL_DUPLEX = 0x01;
910 enum PXE_ENABLE_FUL_DUPLEX = 0x02;
911 enum PXE_FORCE_HALF_DUPLEX = 0x04;
912 enum PXE_DISABLE_FUL_DUPLEX = 0x08;
913 enum LOOPBACK_NORMAL = 0;
914 enum LOOPBACK_INTERNAL = 1;
915 enum LOOPBACK_EXTERNAL = 2;
916 struct PXE_DB_INITIALIZE
917 {
918 align(1):
919     ///
920     /// Actual amount of memory used from the supplied memory buffer.  This
921     /// may be less that the amount of memory suppllied and may be zero if
922     /// the UNDI and network device do not use external memory buffers.
923     ///
924     /// Memory used by the UNDI and network device is allocated from the
925     /// lowest memory buffer address.
926     ///
927     PXE_UINT32 MemoryUsed;
928     ///
929     /// Actual number and size of receive and transmit buffers that were
930     /// allocated.
931     ///
932     PXE_UINT16 TxBufCnt;
933     PXE_UINT16 TxBufSize;
934     PXE_UINT16 RxBufCnt;
935     PXE_UINT16 RxBufSize;
936 }
937 
938 struct PXE_CPB_RECEIVE_FILTERS
939 {
940 align(1):
941     ///
942     /// List of multicast MAC addresses.  This list, if present, will
943     /// replace the existing multicast MAC address filter list.
944     ///
945     PXE_MAC_ADDR[MAX_MCAST_ADDRESS_CNT] MCastList;
946 }
947 
948 struct PXE_DB_RECEIVE_FILTERS
949 {
950 align(1):
951     ///
952     /// Filtered multicast MAC address list.
953     ///
954     PXE_MAC_ADDR[MAX_MCAST_ADDRESS_CNT] MCastList;
955 }
956 
957 struct PXE_CPB_STATION_ADDRESS
958 {
959 align(1):
960     ///
961     /// If supplied and supported, the current station MAC address
962     /// will be changed.
963     ///
964     PXE_MAC_ADDR StationAddr;
965 }
966 
967 struct PXE_DB_STATION_ADDRESS
968 {
969 align(1):
970     ///
971     /// Current station MAC address.
972     ///
973     PXE_MAC_ADDR StationAddr;
974     ///
975     /// Station broadcast MAC address.
976     ///
977     PXE_MAC_ADDR BroadcastAddr;
978     ///
979     /// Permanent station MAC address.
980     ///
981     PXE_MAC_ADDR PermanentAddr;
982 }
983 
984 struct PXE_DB_STATISTICS
985 {
986 align(1):
987     ///
988     /// Bit field identifying what statistic data is collected by the
989     /// UNDI/NIC.
990     /// If bit 0x00 is set, Data[0x00] is collected.
991     /// If bit 0x01 is set, Data[0x01] is collected.
992     /// If bit 0x20 is set, Data[0x20] is collected.
993     /// If bit 0x21 is set, Data[0x21] is collected.
994     /// Etc.
995     ///
996     PXE_UINT64 Supported;
997     ///
998     /// Statistic data.
999     ///
1000     PXE_UINT64[64] Data;
1001 }
1002 /// Total number of frames received.  Includes frames with errors and
1003 /// dropped frames.
1004 enum PXE_STATISTICS_RX_TOTAL_FRAMES = 0x00;
1005 /// Number of valid frames received and copied into receive buffers.
1006 enum PXE_STATISTICS_RX_GOOD_FRAMES = 0x01;
1007 /// Number of frames below the minimum length for the media.
1008 /// This would be <64 for ethernet.
1009 enum PXE_STATISTICS_RX_UNDERSIZE_FRAMES = 0x02;
1010 /// Number of frames longer than the maxminum length for the
1011 /// media.  This would be >1500 for ethernet.
1012 enum PXE_STATISTICS_RX_OVERSIZE_FRAMES = 0x03;
1013 /// Valid frames that were dropped because receive buffers were full.
1014 enum PXE_STATISTICS_RX_DROPPED_FRAMES = 0x04;
1015 /// Number of valid unicast frames received and not dropped.
1016 enum PXE_STATISTICS_RX_UNICAST_FRAMES = 0x05;
1017 /// Number of valid broadcast frames received and not dropped.
1018 enum PXE_STATISTICS_RX_BROADCAST_FRAMES = 0x06;
1019 /// Number of valid mutlicast frames received and not dropped.
1020 enum PXE_STATISTICS_RX_MULTICAST_FRAMES = 0x07;
1021 /// Number of frames w/ CRC or alignment errors.
1022 enum PXE_STATISTICS_RX_CRC_ERROR_FRAMES = 0x08;
1023 /// Total number of bytes received.  Includes frames with errors
1024 /// and dropped frames.
1025 enum PXE_STATISTICS_RX_TOTAL_BYTES = 0x09;
1026 /// Transmit statistics.
1027 enum PXE_STATISTICS_TX_TOTAL_FRAMES = 0x0A;
1028 enum PXE_STATISTICS_TX_GOOD_FRAMES = 0x0B;
1029 enum PXE_STATISTICS_TX_UNDERSIZE_FRAMES = 0x0C;
1030 enum PXE_STATISTICS_TX_OVERSIZE_FRAMES = 0x0D;
1031 enum PXE_STATISTICS_TX_DROPPED_FRAMES = 0x0E;
1032 enum PXE_STATISTICS_TX_UNICAST_FRAMES = 0x0F;
1033 enum PXE_STATISTICS_TX_BROADCAST_FRAMES = 0x10;
1034 enum PXE_STATISTICS_TX_MULTICAST_FRAMES = 0x11;
1035 enum PXE_STATISTICS_TX_CRC_ERROR_FRAMES = 0x12;
1036 enum PXE_STATISTICS_TX_TOTAL_BYTES = 0x13;
1037 /// Number of collisions detection on this subnet.
1038 enum PXE_STATISTICS_COLLISIONS = 0x14;
1039 /// Number of frames destined for unsupported protocol.
1040 enum PXE_STATISTICS_UNSUPPORTED_PROTOCOL = 0x15;
1041 struct PXE_CPB_MCAST_IP_TO_MAC
1042 {
1043 align(1):
1044     ///
1045     /// Multicast IP address to be converted to multicast MAC address.
1046     ///
1047     PXE_IP_ADDR IP;
1048 }
1049 
1050 struct PXE_DB_MCAST_IP_TO_MAC
1051 {
1052 align(1):
1053     ///
1054     /// Multicast MAC address.
1055     ///
1056     PXE_MAC_ADDR MAC;
1057 }
1058 
1059 struct PXE_CPB_NVDATA_SPARSE
1060 {
1061 align(1):
1062     ///
1063     /// NvData item list.  Only items in this list will be updated.
1064     ///
1065     /* FIX:NESTED STRUCTURES */
1066     struct Item_
1067     {
1068         ///
1069         ///  Non-volatile storage address to be changed.
1070         ///
1071         PXE_UINT32 Addr;
1072         ///
1073         /// Data item to write into above storage address.
1074         ///
1075         union Data
1076         {
1077             PXE_UINT8 Byte;
1078             PXE_UINT16 Word;
1079             PXE_UINT32 Dword;
1080         }
1081     }
1082 
1083     Item_[MAX_EEPROM_LEN] Item;
1084 }
1085 /// When using bulk update, the size of the CPB structure must be
1086 /// the same size as the non-volatile NIC storage.
1087 union PXE_CPB_NVDATA_BULK
1088 {
1089     ///
1090     /// Array of byte-wide data items.
1091     ///
1092     PXE_UINT8[MAX_EEPROM_LEN << 2] Byte;
1093     ///
1094     /// Array of word-wide data items.
1095     ///
1096     PXE_UINT16[MAX_EEPROM_LEN << 1] Word;
1097     ///
1098     /// Array of dword-wide data items.
1099     ///
1100     PXE_UINT32[MAX_EEPROM_LEN] Dword;
1101 }
1102 
1103 struct PXE_DB_NVDATA
1104 {
1105 align(1):
1106     ///
1107     /// Arrays of data items from non-volatile storage.
1108     ///
1109     union Data
1110     {
1111         ///
1112         /// Array of byte-wide data items.
1113         ///
1114         PXE_UINT8[MAX_EEPROM_LEN << 2] Byte;
1115         ///
1116         /// Array of word-wide data items.
1117         ///
1118         PXE_UINT16[MAX_EEPROM_LEN << 1] Word;
1119         ///
1120         /// Array of dword-wide data items.
1121         ///
1122         PXE_UINT32[MAX_EEPROM_LEN] Dword;
1123     }
1124 }
1125 
1126 struct PXE_DB_GET_STATUS
1127 {
1128 align(1):
1129     ///
1130     /// Length of next receive frame (header + data).  If this is zero,
1131     /// there is no next receive frame available.
1132     ///
1133     PXE_UINT32 RxFrameLen;
1134     ///
1135     /// Reserved, set to zero.
1136     ///
1137     PXE_UINT32 reserved;
1138     ///
1139     ///  Addresses of transmitted buffers that need to be recycled.
1140     ///
1141     PXE_UINT64[MAX_XMIT_BUFFERS] TxBuffer;
1142 }
1143 
1144 struct PXE_CPB_FILL_HEADER
1145 {
1146 align(1):
1147     ///
1148     /// Source and destination MAC addresses.  These will be copied into
1149     /// the media header without doing byte swapping.
1150     ///
1151     PXE_MAC_ADDR SrcAddr;
1152     PXE_MAC_ADDR DestAddr;
1153     ///
1154     /// Address of first byte of media header.  The first byte of packet data
1155     /// follows the last byte of the media header.
1156     ///
1157     PXE_UINT64 MediaHeader;
1158     ///
1159     /// Length of packet data in bytes (not including the media header).
1160     ///
1161     PXE_UINT32 PacketLen;
1162     ///
1163     /// Protocol type.  This will be copied into the media header without
1164     /// doing byte swapping.  Protocol type numbers can be obtained from
1165     /// the Assigned Numbers RFC 1700.
1166     ///
1167     PXE_UINT16 Protocol;
1168     ///
1169     /// Length of the media header in bytes.
1170     ///
1171     PXE_UINT16 MediaHeaderLen;
1172 }
1173 
1174 enum PXE_PROTOCOL_ETHERNET_IP = 0x0800;
1175 enum PXE_PROTOCOL_ETHERNET_ARP = 0x0806;
1176 enum MAX_XMIT_FRAGMENTS = 16;
1177 struct PXE_CPB_FILL_HEADER_FRAGMENTED
1178 {
1179 align(1):
1180     ///
1181     /// Source and destination MAC addresses.  These will be copied into
1182     /// the media header without doing byte swapping.
1183     ///
1184     PXE_MAC_ADDR SrcAddr;
1185     PXE_MAC_ADDR DestAddr;
1186     ///
1187     /// Length of packet data in bytes (not including the media header).
1188     ///
1189     PXE_UINT32 PacketLen;
1190     ///
1191     /// Protocol type.  This will be copied into the media header without
1192     /// doing byte swapping.  Protocol type numbers can be obtained from
1193     /// the Assigned Numbers RFC 1700.
1194     ///
1195     PXE_MEDIA_PROTOCOL Protocol;
1196     ///
1197     /// Length of the media header in bytes.
1198     ///
1199     PXE_UINT16 MediaHeaderLen;
1200     ///
1201     /// Number of packet fragment descriptors.
1202     ///
1203     PXE_UINT16 FragCnt;
1204     ///
1205     /// Reserved, must be set to zero.
1206     ///
1207     PXE_UINT16 reserved;
1208     ///
1209     /// Array of packet fragment descriptors.  The first byte of the media
1210     /// header is the first byte of the first fragment.
1211     ///
1212     struct Frag_
1213     {
1214         ///
1215         /// Address of this packet fragment.
1216         ///
1217         PXE_UINT64 FragAddr;
1218         ///
1219         /// Length of this packet fragment.
1220         ///
1221         PXE_UINT32 FragLen;
1222         ///
1223         /// Reserved, must be set to zero.
1224         ///
1225         PXE_UINT32 reserved;
1226     }
1227 
1228     Frag_[MAX_XMIT_FRAGMENTS] FragDesc;
1229 }
1230 
1231 struct PXE_CPB_TRANSMIT
1232 {
1233 align(1):
1234     ///
1235     /// Address of first byte of frame buffer.  This is also the first byte
1236     /// of the media header.
1237     ///
1238     PXE_UINT64 FrameAddr;
1239     ///
1240     /// Length of the data portion of the frame buffer in bytes.  Do not
1241     /// include the length of the media header.
1242     ///
1243     PXE_UINT32 DataLen;
1244     ///
1245     /// Length of the media header in bytes.
1246     ///
1247     PXE_UINT16 MediaheaderLen;
1248     ///
1249     /// Reserved, must be zero.
1250     ///
1251     PXE_UINT16 reserved;
1252 }
1253 
1254 struct PXE_CPB_TRANSMIT_FRAGMENTS
1255 {
1256 align(1):
1257     ///
1258     /// Length of packet data in bytes (not including the media header).
1259     ///
1260     PXE_UINT32 FrameLen;
1261     ///
1262     /// Length of the media header in bytes.
1263     ///
1264     PXE_UINT16 MediaheaderLen;
1265     ///
1266     /// Number of packet fragment descriptors.
1267     ///
1268     PXE_UINT16 FragCnt;
1269     ///
1270     /// Array of frame fragment descriptors.  The first byte of the first
1271     /// fragment is also the first byte of the media header.
1272     ///
1273     static struct Frag_
1274     {
1275         ///
1276         /// Address of this frame fragment.
1277         ///
1278         PXE_UINT64 FragAddr;
1279         ///
1280         /// Length of this frame fragment.
1281         ///
1282         PXE_UINT32 FragLen;
1283         ///
1284         /// Reserved, must be set to zero.
1285         ///
1286         PXE_UINT32 reserved;
1287     }
1288 
1289     Frag_[MAX_XMIT_FRAGMENTS] FragDesc;
1290 }
1291 
1292 struct PXE_CPB_RECEIVE
1293 {
1294 align(1):
1295     ///
1296     /// Address of first byte of receive buffer.  This is also the first byte
1297     /// of the frame header.
1298     ///
1299     PXE_UINT64 BufferAddr;
1300     ///
1301     /// Length of receive buffer.  This must be large enough to hold the
1302     /// received frame (media header + data).  If the length of smaller than
1303     /// the received frame, data will be lost.
1304     ///
1305     PXE_UINT32 BufferLen;
1306     ///
1307     /// Reserved, must be set to zero.
1308     ///
1309     PXE_UINT32 reserved;
1310 }
1311 
1312 struct PXE_DB_RECEIVE
1313 {
1314 align(1):
1315     ///
1316     /// Source and destination MAC addresses from media header.
1317     ///
1318     PXE_MAC_ADDR SrcAddr;
1319     PXE_MAC_ADDR DestAddr;
1320     ///
1321     /// Length of received frame.  May be larger than receive buffer size.
1322     /// The receive buffer will not be overwritten.  This is how to tell
1323     /// if data was lost because the receive buffer was too small.
1324     ///
1325     PXE_UINT32 FrameLen;
1326     ///
1327     /// Protocol type from media header.
1328     ///
1329     PXE_MEDIA_PROTOCOL Protocol;
1330     ///
1331     /// Length of media header in received frame.
1332     ///
1333     PXE_UINT16 MediaHeaderLen;
1334     ///
1335     /// Type of receive frame.
1336     ///
1337     PXE_FRAME_TYPE Type;
1338     ///
1339     /// Reserved, must be zero.
1340     ///
1341     PXE_UINT8[7] reserved;
1342 }